Patents by Inventor Lin Wang

Lin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method for fabricating the same
    Patent number: 11778922
    Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: October 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Poor foundation reinforcement system and reinforcement method based on underground concealed arch structures
    Patent number: 11773560
    Abstract: A poor foundation reinforcement system and a reinforcement method based on underground concealed arch structures are provided. The system and the method belong to the technical field of poor foundation treatment. The reinforcement system includes multiple columns of pile foundations arranged along a bridge direction. Multiple arch sheets are set in parallel between each two adjacent columns of pile foundations. Each arch sheet includes multiple high-pressure rotary jet piles arranged along the bridge. Each two adjacent arch sheets of the multiple arch sheets are connected by a micro-bending slab disposed on the two adjacent arch sheets, the multiple arch sheets are connected by the micro-bending slabs to together form an arch ring, and a construction joint is disposed between each two adjacent micro-bending slabs of the micro-bending slabs.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: October 3, 2023
    Assignees: SHANDONG UNIVERSITY, SHANDONG HI-SPEED GROUP CO., LTD.
    Inventors: Renjuan Sun, Chuan Wang, Yanhua Guan, Yonghao Li, Peizhi Zhuang, Huaqiang Yuan, Hongzhi Zhang, Linglai Bu, Yifan Li, Yuhe Tian, Lin Wang
  • Semiconductor device and method for fabricating the same
    Patent number: 11778920
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: October 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Solid particle, preparation method therefor, and pharmaceutical composition containing solid particle
    Patent number: 11771690
    Abstract: A solid particle, a preparation method therefor, and a pharmaceutical composition. The solid particle comprises a porous solid particle and a non-aqueous liquid formula. The non-aqueous liquid formula comprises 0.10-4.00 wt % of a hydrophobic active pharmaceutical agent, 28.00-99.90 wt % of a hydrophobic solubilizing solution, 0-70.00 wt % of a non-ionic surfactant, and 0-1.00 wt % of an antioxidant. The hydrophobic solubilizing solution comprises a medium-chain monoglyceride and diglyceride, and/or a propylene glycol fatty acid monoester.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: October 3, 2023
    Assignee: SHANGHAI WD PHARMACEUTICAL CO., LTD
    Inventors: Liang Chang Dong, Wenbo Ma, Lin Wang
  • Online cleaning system for micro-polluted nanofiltration membranes using forward osmosis and process of online cleaning system
    Patent number: 11772050
    Abstract: An online cleaning system for micro-polluted nanofiltration membranes uses forward osmosis, and a process of the online cleaning system, and relates to the field of water treatment membrane separation technique. The online cleaning system includes a nanofiltration raw water tank, a nanofiltration membrane assembly, a pure water tank, a forward osmosis feed solution tank, a forward osmosis draw solution tank, a first saline water tank, a second saline water tank and a water bath temperature control device. Some embodiments include cleaning of the nanofiltration membranes that is realized by using forward osmosis as a nanofiltration membrane cleaning system, and cyclic regeneration of the nanofiltration membranes can be realized, so that the purposes of removing dissolved organic matters in micro-polluted raw water, reducing hardness of calcium and magnesium and prolonging the service life can be achieved.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: October 3, 2023
    Assignee: Shandong Jianzhu University
    Inventors: Lin Wang, Feiyong Chen, Daoji Wu, Xiaozhen Lu, Qingyan Xia, Tianyu Chen, Juan Zhang, Lu Zhao, Zhihao Li, Bo Gui
  • Memory device
    Patent number: 11778923
    Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.
    Type: Grant
    Filed: November 14, 2021
    Date of Patent: October 3, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Jui Tsou, Zong-You Luo, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
  • CONTROL METHOD, SEMICONDUCTOR MEMORY, AND ELECTRONIC DEVICE
    Publication number: 20230307083
    Abstract: A control method includes: decoding a third Operand (OP) in a third Mode Register (MR) and a fourth OP in a first MR; and in response to the semiconductor memory being in a preset test mode, controlling, in a case where the third OP meets a first decoding condition, the impedance of a Data Mask (DM) pin to be a first value; or controlling, in a case where the third OP meets a second decoding condition, the impedance of the DM pin to be a second value according to the fourth OP; wherein the third OP is configured to indicate whether the DM pin is a test object in the preset test mode, and the fourth OP is configured to indicate whether the DM pin is enabled.
    Type: Application
    Filed: January 18, 2023
    Publication date: September 28, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yoonjoo Eom, Lin Wang, Zhiqiang Zhang, Yuanyuan Gong
  • CONTROL METHOD, SEMICONDUCTOR MEMORY, AND ELECTRONIC DEVICE
    Publication number: 20230307082
    Abstract: An impedance control strategy for a Data Mask Pin (DM pin) in a preset test mode is provided, so that the impedance of the DM pin in the preset test mode may be defined. In addition, the relation between a control signal configured to control whether to enable the DM pin in a Double Data Rate 5 SDRAM (DDR5) and a control signal configured to control whether the DM pin is a test object in a Package Output Driver Test Mode (PODTM) is specified. The impedance of the DM pin may be tested in the preset test mode.
    Type: Application
    Filed: January 17, 2023
    Publication date: September 28, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: YOONJOO EOM, Lin WANG, Zhiqiang ZHANG, Yuanyuan GONG
  • CONTROL METHOD, SEMICONDUCTOR MEMORY, AND ELECTRONIC DEVICE
    Publication number: 20230307081
    Abstract: Embodiments of the present disclosure provide a control method, a semiconductor memory, and an electronic device. When the semiconductor memory is in a preset test mode, a first Model Register (MR) and a second MR related to a Data Pin (DQ) are allowed to directly define the impedance of a Data Mask Pin (DM). The DM does not need to add definition of an output driver state and a related control circuit for the preset test mode to ensure that the preset test mode is adapted to the DM. The impedance of the DM may be tested in the preset test mode to avoid circuit processing errors.
    Type: Application
    Filed: January 17, 2023
    Publication date: September 28, 2023
    Inventors: YoonJoo EOM, Lin WANG, Zhiqiang ZHANG, Yuanyuan GONG
  • MAGNETORESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20230309414
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 28, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
  • Projection screen and projection system
    Patent number: 11762275
    Abstract: A projection screen and a projection system. The projection screen includes a reflection layer and a light absorption layer for absorbing light which are sequentially arranged from an incident side of projection light; the reflection layer comprises multiple microstructure units; each microstructure unit comprises a first plane and a second plane which are opposite to each other at an angle in a first direction as well as a third plane and a fourth plane which are opposite to each other at an angle in a second direction.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 19, 2023
    Assignee: APPOTRONICS CORPORATION LIMITED
    Inventors: Wei Sun, Lin Wang, Zeda Tang, Fei Hu, Yi Li
  • Semiconductor Device
    Publication number: 20230292627
    Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 14, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Yi-Yu Lin, Ching-Hua Hsu, Hung-Yueh Chen
  • POOR FOUNDATION REINFORCEMENT SYSTEM AND REINFORCEMENT METHOD BASED ON UNDERGROUND CONCEALED ARCH STRUCTURES
    Publication number: 20230279632
    Abstract: A poor foundation reinforcement system and a reinforcement method based on underground concealed arch structures are provided. The system and the method belong to the technical field of poor foundation treatment. The reinforcement system includes multiple columns of pile foundations arranged along a bridge direction. Multiple arch sheets are set in parallel between each two adjacent columns of pile foundations. Each arch sheet includes multiple high-pressure rotary jet piles arranged along the bridge. Each two adjacent arch sheets of the multiple arch sheets are connected by a micro-bending slab disposed on the two adjacent arch sheets, the multiple arch sheets are connected by the micro-bending slabs to together form an arch ring, and a construction joint is disposed between each two adjacent micro-bending slabs of the micro-bending slabs.
    Type: Application
    Filed: February 15, 2023
    Publication date: September 7, 2023
    Inventors: Renjuan Sun, Chuan Wang, Yanhua Guan, Yonghao Li, Peizhi Zhuang, Huaqiang Yuan, Hongzhi Zhang, Linglai Bu, Yifan Li, Yuhe Tian, Lin Wang
  • MICROBUBBLE COUNTING METHOD FOR PATENT FORAMEN OVALE (PFO) BASED ON DEEP LEARNING
    Publication number: 20230281806
    Abstract: A microbubble counting method for patent foramen ovale (PFO) based on deep learning is provided. The method includes: segmenting a target area of a left heart in an ultrasonic image; and generating a corresponding density map for a segmented target image using a convolutional neural network (CNN), and calculating a total number of the microbubbles in the segmented area by integration and summation. The method has the following beneficial effects: target segmentation is performed on the left atrium and left ventricular area of the heart using the neural network, and effective segmentation of the target area of the left heart is the key of obtaining parameters such as a size and form of the target area. The target area is quantitatively analyzed according to a segmentation result, and the number of the microbubbles in the target area is counted.
    Type: Application
    Filed: February 28, 2023
    Publication date: September 7, 2023
    Applicant: Henan University of Science and Technology
    Inventors: Mingchuan ZHANG, Mengjie GU, Lin WANG, Qingtao WU, Junlong ZHU, Zhihang JI
  • Magnetoresistive memory device and manufacturing method thereof
    Patent number: 11749328
    Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 5, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Zong-You Luo, Ya-Jui Tsou, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
  • Manufacturing method of semiconductor device
    Patent number: 11751482
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: September 5, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Yi Weng, Jing-Yin Jhang, Hui-Lin Wang, Chin-Yang Hsieh
  • Curved screen and method of arranging microstructure therein, and projection system
    Patent number: 11740545
    Abstract: A curved screen comprises the following layers sequentially arranged from inside to outside: a black light-absorbing layer, a microstructure array layer, and a transparent matrix layer. The microstructure array layer consists of a plurality of microstructure units. The microstructure unit is a V-shaped recess consisting of two intersecting inclined surfaces. The microstructure array layer is rotationally symmetrical with respect to a center line of the curved screen. Angles of the V-shaped recesses in respective longitudinal cross sections of the curved screen are uniquely determined according to incident angles of light rays from a projector. Also disclosed are a method of arranging microstructures in the curved screen and a projection system comprising the curved screen. The curved screen has a higher contrast, improved brightness uniformity and an enlarged field of view.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: August 29, 2023
    Assignee: Appotronics Corporation Limited
    Inventors: Lin Wang, Fei Hu, Yi Li
  • SALT OF DEMETHYL TRAMADOL AND USE THEREOF
    Publication number: 20230265044
    Abstract: The present invention provides a salt of demethyl tramadol, i.e., a compound represented by formula (I) or a solvate thereof, a pharmaceutical composition comprising the compound represented by formula (I) or the solvate thereof, and a use of the compound represented by formula (I) or the solvate thereof or the pharmaceutical composition in the treatment of moderate to severe pain. The compound or pharmaceutical composition of the present invention can stably release a drug having analgesic activity in a body for a long period of time, can be conveniently used by doctors and patients while exerting pharmacological effects, and has good medication compliance.
    Type: Application
    Filed: June 25, 2021
    Publication date: August 24, 2023
    Inventors: Fei LIU, Gang WU, Xiaobo WANG, Yehai XU, Lin WANG, Minqiang ZHENG
  • Sensing cell and sensing device
    Patent number: 11733203
    Abstract: A sensing cell includes: a first electrode coupled to a gate of a transistor, a second electrode spaced apart from the first electrode; a protective layer covering sidewalls of the first electrode and the second electrode and having a first opening and a second opening exposing a first part of the first electrode and a second part of the second electrode, respectively; a first well located on the protective layer and surrounding the first electrode and the second electrode and having a third opening exposing the first part of the first electrode, the second part of the second electrode, and the protective layer between the first opening and the second opening; a second well located on the protective layer surrounding the first well and having a fourth opening to limit a flow of a liquid to be tested; and an ion selective membrane located in the third opening.
    Type: Grant
    Filed: January 24, 2021
    Date of Patent: August 22, 2023
    Assignee: National Tsing Hua University
    Inventors: Yu-Lin Wang, Shin-Li Wang
  • Magnetoresistive random access memory (MRAM) device
    Patent number: 11737370
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: August 22, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang