Abstract: A semiconductor device includes a first metal interconnection on a substrate, a first inter-metal dielectric (IMD) layer around the first metal interconnection, an electromigration enhancing layer on the first metal interconnection, a second IMD layer on and around the electromigration enhancing layer, and a second metal interconnection on the electromigration enhancing layer.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

Abstract: A method for forming a multi-material part by selective laser melting includes the following steps. Modeling is performed by regularly distributing and arraying a combination of materials that meets forming requirements such that a part model is designed. The designed part model is subjected to a dimension compensation, a shape compensation, a chamfering setting, a margin design and a design of a process support to obtain a process model. The obtained process model is sliced into a series of layers. Type, distribution and boundary information of materials in each layer are collected to generate a control file. All materials required for part forming are loaded into an additive manufacturing equipment. After a state of the additive manufacturing equipment meets forming requirements, a part is formed under the control of the generated control file. Post-processing is performed after the part is formed.

Abstract: There are provided compounds of Formula (A) and pharmaceutically acceptable salts and esters thereof, and pharmaceutical compositions thereof, used for the prevention or treatment in a mammal of joint and bone disorders such as arthritis and osteoporosis.

Abstract: The present disclosure relates to a crystal form of a pyridopyrimidine derivative and a preparation method thereof, and specifically relates to the crystal form of the compound of formula (I) and a preparation method thereof. The new crystal form has good physical and chemical properties, thereby facilitating clinical treatments.

Abstract: Provided are variant adenosine deaminase 2 (ADA2) proteins, conjugates thereof and compositions containing the proteins and/or conjugates. Also provided are methods and uses of the ADA2 proteins or conjugates for treating diseases and conditions, such as a tumor or cancer, and in particular any disease or condition associated with elevated adenosine or other associated marker.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A display apparatus including a circuit board, a plurality of light-emitting devices and a display panel is provided. The light-emitting devices are disposed on the circuit board and electrically connected to the circuit board. The display panel is disposed on the light-emitting devices. The display panel includes a peripheral light-shielding pattern. An opening portion of the peripheral light-shielding pattern defines an active area of the display panel. A physical portion of the peripheral light-shielding pattern defines a non-active area of the display panel. An optical axis of a light-emitting surface of at least one of the light-emitting devices is located at a junction of the active area and the non-active area, at the non-active area, or at the active area and a side wall of the at least one of the light-emitting devices is located at the junction of the active area and the non-active area.

Abstract: The present disclosure provides a control method for an AC-DC conversion circuit. The method includes: in an entire load range, acquiring circuit parameter information of the AC-DC conversion circuit; limiting an actual switching frequency or an actual switching period of the AC-DC conversion circuit within a preset working range according to the circuit parameter information. The AC-DC conversion circuit can meet requirements of Total Harmonic Distortion (THD), Power Factor (PF), efficiency and Electromagnetic Interference (EMI) and the like by adjusting the working information of the AC-DC conversion circuit through the preset working range.

Abstract: An apparatus comprising a substrate, one or more nanowire pillars, each having a base portion and a tip portion, a first electrode connected to the tip portions of the one or more nanowire pillars, an internal hollow cavity positioned between the substrate and the first electrode, such that at least a portion of each of the one or more nanowire pillars extend through the internal hollow cavity, and a second electrode proximate the first side of the substrate. High-performance broadband photodetectors and other optoelectronics for converting light to electricity with enhanced absorption and carrier collection.

Abstract: A method for achieving sintering of ceramics at room temperature is disclosed. The method includes steps of: providing ceramic green body; placing the ceramic green body into a sealed container containing water vapor to cause the ceramic green body to soak up the water vapor to obtain an aqueous ceramic green body; removing the aqueous ceramic green body from the sealed container, and connecting a power supply to the aqueous ceramic green body; applying a voltage to the aqueous ceramic green body; and increasing the voltage to a predetermined voltage value to cause a surface discharge or an internal discharge to occur on the aqueous ceramic green body, and stopping the power supply after a predetermined time, thereby obtaining a ceramic. A ceramic formed by the method is also disclosed.

Abstract: A memory device includes a spin-orbit-transfer (SOT) bottom electrode, an SOT ferromagnetic free layer, a first tunnel barrier layer, a spin-transfer-torque (STT) ferromagnetic free layer, a second tunnel barrier layer and a reference layer. The SOT ferromagnetic free layer is over the SOT bottom electrode. The SOT ferromagnetic free layer has a magnetic orientation switchable by the SOT bottom electrode using a spin Hall effect or Rashba effect. The first tunnel barrier layer is over the SOT ferromagnetic free layer. The STT ferromagnetic free layer is over the first tunnel barrier layer and has a magnetic orientation switchable using an STT effect. The second tunnel barrier layer is over the STT ferromagnetic free layer. The second tunnel barrier layer has a thickness different from a thickness of the first tunnel barrier layer. The reference layer is over the second tunnel barrier layer and has a fixed magnetic orientation.

Abstract: Some implementations described herein provide a shutter disc for use during a conditioning process within a processing chamber of a deposition tool. The shutter disc described herein includes a material having a wave-shaped section to reduce heat transfer to the shutter disc and to provide relief from thermal stresses. Furthermore, the shutter disc includes a deposition of a thin-film material on a backside of the shutter disc, where a diameter of the shutter disc causes a spacing between an inner edge of the thin-film material and an outer edge of a substrate support component. The spacing prevents an accumulation of material between the thin film material and the substrate support component, reduces tilting of the shutter disc due to a placement error, and reduces heat transfer to the shutter disc.

Abstract: A foam production method includes mixing liquid nitrogen with a foaming material to produce foam. A gas is produced in situ from liquid nitrogen. As the ratio of the volume of the gas produced by gasification of liquid nitrogen to the volume of the liquid nitrogen is relatively high, when a large gas supply flow is needed to generate a large foam flow, a liquid nitrogen storage device of a small volume can be used instead of bulky air supply devices such as high-pressure gas cylinders, air compressors, air compressor sets and the like, reducing the volume of the air supply device. In addition, the liquid nitrogen used in foaming will release nitrogen gas after the foam blast, such that the nitrogen is also able to inhibit combustion on the surface of burning materials, accelerating the extinguishing of the fire.

Abstract: A layout structure of an anti-fuse array at least includes an array circuit area and a functional circuit area. The array circuit area is electrically connected with the functional circuit area. The functional circuit area is located on at least one side of the array circuit area, and at least one side of the array circuit area is located on an edge of the layout structure. The array circuit area includes an anti-fuse array composed of anti-fuse cells, and the array circuit area is configured to provide the anti-fuse cells under different column addresses to the functional circuit area. The functional circuit area is configured to fuse the anti-fuse cells under the different column addresses.