Patents by Inventor Lin Wang

Lin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11733203
    Abstract: A sensing cell includes: a first electrode coupled to a gate of a transistor, a second electrode spaced apart from the first electrode; a protective layer covering sidewalls of the first electrode and the second electrode and having a first opening and a second opening exposing a first part of the first electrode and a second part of the second electrode, respectively; a first well located on the protective layer and surrounding the first electrode and the second electrode and having a third opening exposing the first part of the first electrode, the second part of the second electrode, and the protective layer between the first opening and the second opening; a second well located on the protective layer surrounding the first well and having a fourth opening to limit a flow of a liquid to be tested; and an ion selective membrane located in the third opening.
    Type: Grant
    Filed: January 24, 2021
    Date of Patent: August 22, 2023
    Assignee: National Tsing Hua University
    Inventors: Yu-Lin Wang, Shin-Li Wang
  • Patent number: 11736390
    Abstract: Techniques for enhanced Software-Defined Wide Area Network (SD-WAN) path quality measurement and selection are disclosed. In some embodiments, a system/method/computer program product for enhanced SD-WAN path quality measurement and selection includes periodically performing a network path measurement for each of a plurality of network paths at a Software-Defined Wide Area Network (SD-WAN) interface; updating a version if the network path measurement exceeds a threshold for one or more of the plurality of network paths; and selecting one of the plurality of network paths for a session based on the version according to an application policy.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: August 22, 2023
    Assignee: Palo Alto Networks, Inc.
    Inventors: Chunqing Cai, Philip Kwan, Lin Wang, Lei Chang, Sameer Kumar, Pulikeshi Ramanath, Santosh Narayankhedkar
  • Patent number: 11737370
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: August 22, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Publication number: 20230257508
    Abstract: An environmentally-friendly flexible conductive polyurethane (PU) and a preparation method thereof are disclosed. The environmentally-friendly flexible conductive PU is prepared by subjecting a mixture of a component A and a component B in a specified mass ratio to in-situ solvent-free polymerization, where the component A is prepared from a polyol, a T-type chain extender, a diselenide diol, high-conductivity carbon black, a dispersing agent, a catalyst, and a leveling agent, and the component B is prepared from a polyisocyanate, a polyol, a multi-walled carbon nanotube (MWCNT), and a dispersing agent. The PU has a reliable electrically-conductive function, and shows a self-healing function under room temperature or light conditions when damaged, wherein a microphase separation value HBI (0.5 to 3.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 17, 2023
    Applicants: SHAOXING-KEQIAO INSTISUTE OF ZHEJIANG SCI-TECH UNIVERSITY CO., LTD., ZHEJIANG SCI-TECH UNIVERSITY
    Inventors: Dongming QI, Zhichao HUANG, Qianjun TIAN, Lin WANG, Chenghai LIU
  • Publication number: 20230263067
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 17, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Patent number: 11728376
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Wei Lin, Chih-Lin Wang, Kang-Min Kuo
  • Publication number: 20230255122
    Abstract: A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 10, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Wei-Jen CHEN, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Chih-Lin WANG
  • Publication number: 20230253736
    Abstract: A backplane connector includes a shielded design that has wafers with signal terminals supported as edge-coupled terminal pairs for differential signaling. A ground shield is mounted on each wafer and provides a U-channel that partially shields each terminal pair. An insert can be provided to help connect the ground shield to a U-shield to provide U-shaped shielding structure substantially the entire way from a tail to a contact.
    Type: Application
    Filed: April 21, 2023
    Publication date: August 10, 2023
    Inventors: John C. Laurx, Chien-Lin Wang, Vivek Shah
  • Patent number: 11718636
    Abstract: There are provided compounds of Formula (A) and pharmaceutically acceptable salts and esters thereof, and pharmaceutical compositions thereof, used for the prevention or treatment in a mammal of joint and bone disorders such as arthritis and osteoporosis.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 8, 2023
    Assignee: RISEN (SUZHOU) PHARMA TECH CO., LTD.
    Inventors: Xianqi Kong, Jiasheng Lu, Jiamin Gu, Xiang Ji, Daiqiang Hu, Xiuchun Zhang, Xinyong Lv, Jinchao Ai, Dongdong Wu, Lin Wang, Dongqing Zhu, Xiaolin He
  • Publication number: 20230243776
    Abstract: Provided is a coronavirus detection method which is suitable for a coronavirus disease 2019 (COVID-19) detection. The method includes the following steps. A field-effect transistor-based biosensor (BioFET) platform is provided, wherein the BioFET platform includes a BioFET and a sensor card. The sensor card is detachably connected to the BioFET, wherein the sensor card includes a plurality of sensors and each of the plurality of sensors includes a response electrode. A nucleic acid probe specific to a nucleic acid sequence of COVID-19 virus is immobilized on a surface of the response electrode. A test solution is placed on the response electrode of the sensor card. A pulse voltage is applied to the response electrode, and a detection current generated from the sensor card is measured.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 3, 2023
    Applicant: National Tsing Hua University
    Inventors: Yu-Lin Wang, Akhil Kavanal Paulose
  • Patent number: 11716860
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 1, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen, Wei Chen
  • Patent number: 11715499
    Abstract: A MRAM structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with storage units on corresponding active areas, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: August 1, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kai Hsu, Hung-Yueh Chen, Kun-I Chou, Jing-Yin Jhang, Hui-Lin Wang, Yu-Ping Wang
  • Publication number: 20230238043
    Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.
    Type: Application
    Filed: March 28, 2023
    Publication date: July 27, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Publication number: 20230236299
    Abstract: There is provided a time of flight sensor including a light source, a first pixel, a second pixel and a processor. The first pixel generates a first output signal without receiving reflected light from an external object illuminated by the light source. The second pixel generates a second output signal by receiving the reflected light from the external object illuminated by the light source. The processor calculates deviation compensation and deviation correction associated with temperature variation according to the first output signal to accordingly calibrate a distance calculated according to the second output signal.
    Type: Application
    Filed: March 31, 2023
    Publication date: July 27, 2023
    Inventors: TSO-SHENG TSAI, YUEH-LIN CHUNG, SHIN-LIN WANG
  • Publication number: 20230240151
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
    Type: Application
    Filed: March 17, 2023
    Publication date: July 27, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Si-Han Tsai, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang, Yu- Ping Wang, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Publication number: 20230232637
    Abstract: A magnetic memory device includes a bottom electrode layer, a magnetic tunneling junction (MTJ) stack disposed on the bottom electrode layer, a dielectric cap layer disposed on the MTJ stack, and a metal cap layer disposed on the dielectric cap layer, wherein the metal cap layer comprises a plurality of first metal layers and second metal layers alternately stacked on the dielectric cap layer.
    Type: Application
    Filed: February 20, 2022
    Publication date: July 20, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Jing-Yin Jhang
  • Publication number: 20230232638
    Abstract: Abstract of Disclosure A memory array includes at least one strap region, at least two sub-arrays, a plurality of staggered, dummy magnetic storage elements, and a plurality of bit line structures. The strap region includes a plurality of source line straps and a plurality of word line straps. The two sub-arrays include a plurality of staggered, active magnetic storage elements. The two sub -arrays are separated by the strap region. The staggered, dummy magnetic storage elements are disposed within the strap region. The bit line structures are disposed in the two sub-arrays, and each of the bit line structures is disposed above and directly connected with at least one of the staggered, active magnetic storage elements.
    Type: Application
    Filed: February 16, 2022
    Publication date: July 20, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Ju-Chun Fan, Ching-Hua Hsu, Chun-Hao Wang, Yi-Yu Lin, Dong-Ming Wu, Po-Kai Hsu
  • Publication number: 20230227488
    Abstract: There are provided compounds of Formula (A) and pharmaceutically acceptable salts and esters thereof, and pharmaceutical compositions thereof, used for the prevention or treatment in a mammal of joint and bone disorders such as arthritis and osteoporosis.
    Type: Application
    Filed: January 18, 2023
    Publication date: July 20, 2023
    Inventors: Jiasheng LU, Jiamin GU, Xiang JI, Daiqiang HU, Xiuchun ZHANG, Xinyong LV, Jinchao AI, Dongdong WU, Xianqi KONG, LIN WANG, Dongqing ZHU, Xiaolin HE
  • Patent number: 11706993
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: July 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11706996
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: July 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang