Abstract: A semiconductor device includes a storage element on a substrate. The storage element has a tapered upper end structure. The tapered upper end structure includes a top electrode and a spacer surrounding the top electrode. A gap-fill dielectric layer is disposed around the spacer. A conductive cap layer covers the top electrode and the spacer. An inter-metal dielectric (IMD) layer is disposed on the conductive cap layer. A metal interconnection is disposed in the IMD layer and electrically connected to the top electrode through the conductive cap layer.

Abstract: The present invention provides methods and compositions for carrying out nucleic acid sequencing, particularly paired-end sequencing. The methods use concatemeric sequencing templates that can be produced by rolling circle amplification of asymmetric circular nucleic acids having a central double-stranded region comprising a target nucleic acid sequence that is connected at each end to form a circular construct.

Abstract: Disclosed is a method for recovering phosphorus from sludge rich in chemical phosphorus precipitates using a high-protein biomass waste, comprising introducing the sludge rich in chemical phosphorus precipitates into an anaerobic fermenter, adding a certain amount of a high-protein biomass by-product, sealing the fermenter and fermenting for 4-7 days. The method can effectively increase the phosphorus release efficiency from the sludge, and also generate volatile short-chain fatty acids and ammonia nitrogen in high concentrations. After dewatering, phosphorus and part of ammonia nitrogen can be recovered in a form of high-purity struvite crystals only by addition of a magnesium salt and adjustment of pH to 7.5-9.0. The volatile short-chain fatty acids can be used as an economical carbon source. The method allows simultaneous utilization of two solid wastes to recover carbon, nitrogen and phosphorus resources, and can reduce the usage of chemical reagents, saving the treatment cost.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.

Abstract: Provided is an LSTM-based hot-rolling roll-bending force predicting method including the steps of acquiring final rolling data of a stand of a stainless steel rolling mill when performing a hot rolling process, and dividing the data into a training set traindata and a test set testdata; normalizing the traindata; building a matrix P; using a last row of the matrix P as a label of the training set, namely a true value; calculating and updating an output value and the true value of a network; after network training is completed, taking the last m output data of the LSTM network as an input at a next moment, and then obtaining an output of the network at the next moment, wherein the output is a predicted value of the roll-bending force at the next moment; repeating the steps until a sufficient number of prediction data is obtained; and comparing the processed data with the true value in the testdata to check the validity of the network.

Abstract: A driving circuit film configured to be bond at a periphery region of a display panel. The driving circuit film includes a flexible substrate, a gate driving circuit and a source driver. The gate driving circuit is disposed on the flexible substrate, and the gate driving circuit includes a Thin-Film Transistor. The source driver is disposed on the flexible substrate.

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

Abstract: A display apparatus including a circuit board, a plurality of light-emitting devices and a display panel is provided. The light-emitting devices are disposed on the circuit board and electrically connected to the circuit board. The display panel is disposed on the light-emitting devices. The display panel includes a peripheral light-shielding pattern. An opening portion of the peripheral light-shielding pattern defines an active area of the display panel. A physical portion of the peripheral light-shielding pattern defines a non-active area of the display panel. An optical axis of a light-emitting surface of at least one of the light-emitting devices is located at a junction of the active area and the non-active area, at the non-active area, or at the active area and a side wall of the at least one of the light-emitting devices is located at the junction of the active area and the non-active area.

Abstract: An acid addition salt of a ROR? regulator. Specifically relating to the acid addition salt of the compound of formula II. More specifically relating to benzoate, oxalate, methanesulfonate, maleate, hydrobromate, hydrochloride salt, and acetate of the compound of formula II and the benzoate crystal form, benzoate amorphous form, oxalate crystal form, oxalate amorphous form, methanesulfonate amorphous form, maleate B crystal form, maleate C crystal form, maleate D crystal form, hydrobromate I crystal form, hydrochloride salt ? crystal form, hydrochloride salt ? crystal form, hydrochloride salt ? crystal form, and acetate crystal form of the compound of formula II.

Abstract: Provided herein are single-domain antibodies targeting BCMA, and chimeric antigen receptors (such as monovalent CAR, and multivalent CAR including bi-epitope CAR) having one or more anti-BCMA single-domain antibodies. Further provided are engineered immune effector cells (such as T cells) having the chimeric antigen receptors. Pharmaceutical compositions, kits and methods of treating cancer are also provided.

Abstract: A method of washing glassware is provided including: providing automatic dishwashing apparatus; providing soiled glassware; placing soiled glassware in automatic dishwashing apparatus; providing wash water; providing rinse water; selecting anhydrous mixed powder or mixed granule comprising: 2.5-5 wt % of oxidized maltodextrin, wherein oxidized maltodextrin has Degree of Oxidation of 0.4-1.7; 10-25 wt % of amino acid based builder; 20-75 wt % of additional builder, wherein additional builder includes at least one of sodium citrate, sodium carbonate and sodium percarbonate; 2.5-7.5 wt % of bleach activator; 0.5-10 wt % of nonionic surfactant; 0.

Abstract: CD73 (also known as ecto-5?-nucleotidase) inhibitor compounds are provided, as well as compositions and uses thereof for treating or preventing CD73-associated or related diseases, disorders and conditions, including cancer- and immune-related disorders. CD73 inhibitor compounds include compounds having the structure set forth in Formula I and pharmaceutically acceptable esters or salts thereof.

Abstract: An optimization method for an implementation of mel-frequency cepstral coefficients is provided. The optimization method includes the following steps: performing a framing step, including using a 400×16 static random access memory to temporarily store a plurality of sampling points of a sound signal with overlap, and decomposing the sound signal into a plurality of frames. Each of the plurality of frames is 400 of the sampling points, there is an overlapping region between adjacent two of the plurality of frames, and the overlapping region includes 240 of the sampling points. The optimization method further includes performing a windowing step, which includes multiplying each of the plurality of frames by a window function in a bit-level design, and the optimization method includes performing a fast Fourier transform (FFT) step, which includes applying a 512 point FFT on a frame signal to obtain a corresponding frequency spectrum.

Abstract: A graphical structure model trained by using labeled samples is obtained. The graphical structure model is defined based on an enterprise relationship network that includes nodes and edges. Each labeled sample includes a label indicating whether a corresponding node is a risky credit node. The graphical structure model is configured to iteratively calculate an embedding vector of at least one node in a hidden feature space based on an original feature of the at least one node and/or a feature of an edge associated with the at least one node. An embedding vector corresponding to a test-sample is calculated by using the graphical structure model. Credit risk analysis is performed on the test-sample. The credit risk analysis is performed based on a feature of the test-sample represented in the embedding vector. A node corresponding to the test-sample is labeled as a credit risk node.

Abstract: One or more implementations of the present specification provide risk control of transactions based on a graphical structure model. A graphical structure model trained by using labeled samples is obtained. The graphical structure model is defined based on a transaction data network that includes nodes representing entities in a transaction and edges representing relationships between the entities. Each labeled sample includes a label indicating whether a node corresponding to the labeled sample is a risky transaction node. The graphical structure model is configured to iteratively calculate an embedding vector of the node in a latent feature space based on an original feature of the node or a feature of an edge associated with the node. An embedding vector of an input sample is calculated by using the graphical structure model. Transaction risk control is performed on the input sample based on the embedding vector.

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a first magnetic tunneling junction (MTJ) on a substrate, forming a first top electrode on the first MTJ, and then forming a passivation layer around the first MTJ. Preferably, the passivation layer includes a V-shape and a valley point of the V-shape is higher than a top surface of the first top electrode.

Abstract: A transparent projection screen and a manufacturing method. The transparent projection screen is for receiving projection light and transmitting ambient light and comprises a first substrate layer, a Fresnel structure layer, a surface diffusion layer, a nano metal plating layer, and a binding adhesive layer. The Fresnel structure layer is disposed on the first substrate layer and comprises a prism surface. The surface diffusion layer is disposed on a portion of the prism surface. The nano metal plating layer is disposed on the surface diffusion layer. The binding adhesive layer is disposed on the nano metal plating layer and fills and levels the prism surface. The projection light passes the first substrate layer and is incident on the prism surface and then reflected thereby. The ambient light passes the binding adhesive layer, the nano metal plating layer, the surface diffusion layer and the first substrate layer, and is emitted.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.