Patents by Inventor Lin Wang

Lin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220271088
    Abstract: A memory array includes at least one strap region having therein a plurality of source line straps and a plurality of word line straps, and at least two sub-arrays having a plurality of staggered, active magnetic storage elements. The at least two sub-arrays are separated by the strap region. A plurality of staggered, dummy magnetic storage elements is disposed within the strap region.
    Type: Application
    Filed: March 15, 2021
    Publication date: August 25, 2022
    Inventors: Po-Kai Hsu, Hui-Lin Wang, Kun-I Chou, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Hung-Yueh Chen
  • Publication number: 20220268975
    Abstract: A projection screen with a design in which the apexes of multiple triangular pyramidal units of the projection screen in an array arrangement change gradually according to a predetermined relation, an image light shone from a projector is reflected by a microstructure layer having the triangular pyramidal units and then converged in a range centered around the human eyes, so as to reduce the degree of difference in brightness at different viewing positions, thus ensuring that the projection screen is provided with excellent uniformity and high gain.
    Type: Application
    Filed: June 28, 2020
    Publication date: August 25, 2022
    Inventors: Lin WANG, Xiaofeng TANG, Wei SUN, Yi LI
  • Publication number: 20220269159
    Abstract: The present application provides a projection screen and a projection system. The projection screen includes an optical structure layer and a reflective layer, where the optical structure layer includes a plurality of microstructure units; each of the plurality of microstructure units include a first sidewall and second sidewalls; the reflective layer covers at least part of the first sidewall to form a first working surface, and the reflective layer covers at least part of the second sidewalls to form second working surfaces, respectively; the first working surface deflects an input image beam, and at least part of the input image beam is transmitted to viewer's field and the second working surfaces; and the second working surfaces deflect an input image beam came from the first working surface, and the input image beam came from the first working surface is transmitted to the viewer's field. The present application improves the brightness evenness of the projection screen.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 25, 2022
    Inventors: Lin WANG, Wei SUN, Xiaofeng TANG, Fei HU, Yi LI
  • Patent number: 11419263
    Abstract: A trimmer head having at least two pivoting line holders for holding multiple folded strips of trimming line is presented wherein said pivoting line holders are retained within said housing between said housing and said cover and extend upward through apertures in said cover, said line holders being capable of movement around a vertical axis of rotation, at least three embodiments are disclosed which provide a rounded landing for supporting the inner radius of a folded strip of trimming line, the rounded geometry of the landing prevents line stress and breakage, the various embodiments include a pivot post having two parallel straight through holes with a rounded vertical wall between the through holes, a single open passageway having a center metal post, and a single open passageway having a series of at least two metal pins through the center of the passageway.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 23, 2022
    Assignee: SHAKESPEARE COMPANY, LLC
    Inventors: David B. Skinner, Brian Searfoss, Wen Liu, Lin Wang, Jack Yang
  • Publication number: 20220263017
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.
    Type: Application
    Filed: May 5, 2022
    Publication date: August 18, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Publication number: 20220262216
    Abstract: A security device system including portions configured to have a combined state and a separated state. In the combined state, circuitry is configured to have an armed state and a not-armed state, and to trigger an alarm during a breach of the armed state. Depending on the embodiment, at least one of the portions, and in some embodiments more than one of the portions, participate in the armed and not-armed states. In some embodiments, the security device system includes an alarm device portion, a cradle portion, and a stratum portion.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Applicant: Hangzhou Timing Security Technologies Co., Ltd.
    Inventors: Hexiao Wang, Peter A. Morello, Jr., Lin Wang, Peter Morello, Sr.
  • Publication number: 20220259646
    Abstract: Compositions and methods labeling individual nucleic acid (e.g., DNA) molecules with a unique molecular identifier (UMI), followed by amplification by PCR are provided. The PCR amplicons can be grouped by the UMI they contain and traced back to the original molecule. More specifically, the grouped reads with the same UMI represent one original nucleic acid (e.g., DNA) molecule, meaning they share the same nucleic acid sequence. Methods of sequencing the labeled nucleic acid are also provided. The methods can include determination of a consensus sequence, which thus eliminates errors that may be introduced in the amplification and sequencing process. Such methods can be used in, for example, the detection of rare genetic variants.
    Type: Application
    Filed: March 4, 2020
    Publication date: August 18, 2022
    Inventors: Mo Li, Chongwei Bi, Lin Wang
  • Publication number: 20220263402
    Abstract: The present disclosure provides a control method for an AC-DC conversion circuit. The method includes: in an entire load range, acquiring circuit parameter information of the AC-DC conversion circuit; limiting an actual switching frequency or an actual switching period of the AC-DC conversion circuit within a preset working range according to the circuit parameter information. The AC-DC conversion circuit can meet requirements of Total Harmonic Distortion (THD), Power Factor (PF), efficiency and Electromagnetic Interference (EMI) and the like by adjusting the working information of the AC-DC conversion circuit through the preset working range.
    Type: Application
    Filed: April 14, 2022
    Publication date: August 18, 2022
    Inventors: Kai DONG, Lin WANG, Shuailin DU, Junhao JI, Hui HUANG
  • Publication number: 20220263016
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 18, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Patent number: 11417838
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 16, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Wei Chen, Po-Kai Hsu, Yu-Ping Wang, Hung-Yueh Chen
  • Patent number: 11410714
    Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: August 9, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Zong-You Luo, Ya-Jui Tsou, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
  • Patent number: 11410035
    Abstract: Disclosed is a real-time object detection method deployed on a platform with limited computing resources, which belongs to the field of deep learning and image processing. In the present invention, YOLO-v3-tiny neural network is improved, Tinier-YOLO reserves the front five convolutional layers and pooling layers of YOLO-v3-tiny and makes prediction at two different scales. Fire modules in SqueezeNet, 1×1 bottleneck layers, and dense connection are introduced, so that the structure is used to achieve smaller, faster, and more lightweight network that can be run in real time on an embedded AI platform. The model size of Tinier-YOLO in the present invention is only 7.9 MB, which is only ¼ of 34.9 MB of YOLO-v3-tiny, and ? of YOLO-v2-tiny. The reduction in the model size of Tinier-YOLO does not affect real-time performance and accuracy of Tinier-YOLO. Real-time performance of Tinier-YOLO in the present invention is 21.8% higher than that of YOLO-v3-tiny and 70.8% higher than that of YOLO-v2-tiny.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: August 9, 2022
    Assignee: Jiangnan University
    Inventors: Wei Fang, Peiming Ren, Lin Wang, Jun Sun, Xiaojun Wu
  • Publication number: 20220243308
    Abstract: A spheroidal graphite cast iron meeting N(5-)?250, N5-20)/N(5-)?0.6, and N(30-)/N(5-)?0.2, wherein N(5-) represents the number (/mm2) of graphite particles having equivalent-circle diameters of 5 ?m or more, N(5-20) represents the number (/mm2) of graphite particles having equivalent-circle diameters of 5 ?m or more and less than 20 ?m, and N(30-) represents the number (/mm2) of graphite particles having equivalent-circle diameters of 30 ?m or more, among graphite particles observed in an arbitrary cross section of at least 1 mm2.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Applicant: Hitachi Metals, Ltd.
    Inventor: Lin WANG
  • Publication number: 20220238793
    Abstract: A semiconductor device includes a synthetic antiferromagnetic (SAF) layer on a substrate, a barrier layer on the SAF layer, and a free layer on the barrier layer. Preferably, the SAF layer further includes a first pinned layer, a first spacer on the first pinned layer, a second pinned layer on the first spacer, a second spacer on the second pinned layer, and a reference layer on the second spacer.
    Type: Application
    Filed: February 23, 2021
    Publication date: July 28, 2022
    Inventors: Wei Chen, Hui-Lin Wang
  • Publication number: 20220238428
    Abstract: A semiconductor structure includes: a pad structure disposed above a substrate; and a capacitor structure which is disposed between the substrate and the pad structure, is arranged to be opposite to the pad structure, and includes at least two capacitor units connected in parallel and spaced apart from each other, each of the capacitor units includes at least one capacitor device.
    Type: Application
    Filed: August 28, 2021
    Publication date: July 28, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Lin WANG
  • Patent number: 11397347
    Abstract: A color filter substrate, a manufacturing method thereof and a display device are disclosed. The color filter substrate includes a base substrate and a plurality of filter units located on the base substrate. Each filter unit includes a photonic crystal layer configured to transmit light of one color, and includes a first photonic crystal sub-layer and a second photonic crystal sub-layer that are stacked in a direction perpendicular to the base substrate.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: July 26, 2022
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lin Wang, Yongzhi Song, Ruirui Wang, Huabin Chen, Xingliang Li, Yang Liu, Yingqiang Gao
  • Publication number: 20220221780
    Abstract: A projection screen includes a substrate with a first substrate surface. The first substrate surface includes a first region and a second region adjacent to the first region. Multiple first wire grid bodies extending in a first direction are provided in the first region. Multiple second wire grid bodies extending in the first direction are provided in the second region. Each first wire grid body includes a first contact surface connected to the substrate and a first surface, and a first angle is formed therebetween. The first angles gradually decrease in a direction from the first region to the second region. Each second wire grid body includes a second contact surface connected to the substrate and a third surface, and a third angle is formed therebetween. The third angles gradually increase in a direction from the first region to the second region.
    Type: Application
    Filed: May 18, 2020
    Publication date: July 14, 2022
    Applicant: APPOTRONICS CORPORATION LIMITED
    Inventors: Shijie LI, Lin WANG, Fei HU, Wei SUN, Yi LI
  • Patent number: 11385346
    Abstract: In one example, this disclosure is directed to a system configured to detect inclement weather in the travel path of a vehicle, determine a recommended maneuver to avoid the inclement weather, and determine the feasibility of the recommended maneuver with respect to any nearby vehicles.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: July 12, 2022
    Assignee: Honeywell International Inc.
    Inventors: Jing Song, Lin Wang, Peng Liu, Wei Cui, Patrick Glaze
  • Patent number: 11387408
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 12, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Publication number: 20220216397
    Abstract: A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang