Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.

Abstract: Provided is a method for preparing a defect-free DDR molecular sieve membrane. Sigma-1 molecular sieve is used as an inducing seed crystal to prepare and obtain a continuous and compact DDR molecular sieve membrane on the surface of a porous ceramic support. An ozone atmosphere or an external field assisted technology is used to remove a template in the pores of the molecular sieve membrane at a low temperature. The invention avoids the formation of intercrystal defects and cracks, an activated DDR molecular sieve membrane has a good selectivity for separating CO2, and the membrane preparation time is significantly reduced.

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.

Abstract: A total reflection screen comprises a light diffusion layer, a total reflection layer and a light absorption layer arranged sequentially from an incidence side of the projected light. The light absorption layer can absorb an incident light. The light diffusion layer is used for increasing a divergence angle of emergent light. The total reflection layer comprises a plurality of microstructure units that is rotationally symmetrical and extends continuously in a plane of the total reflection screen. Each of the microstructure units comprises a first material layer disposed at the side of the light diffusion layer and a second material layer disposed at the side of the light absorption layer. The interface between the first material layer and the second material layer is comprised of two intersecting planes, which are disposed in such a way that the projected light is subjected to total reflection continuously at the two intersecting planes.

Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.

Abstract: A semiconductor device includes an active area having source and drain regions and a channel region between the source and drain regions, an isolation structure surrounding the active area, and a gate structure over the channel region of the active area and over the isolation structure, wherein the isolation structure has a first portion under the gate structure and a second portion free from coverage by the gate structure, and a top of the first portion of the isolation structure is lower than a top of the second portion of the isolation structure.

Abstract: Techniques for enhanced Software-Defined Wide Area Network (SD-WAN) path quality measurement and selection are disclosed. In some embodiments, a system/method/computer program product for enhanced SD-WAN path quality measurement and selection includes periodically performing a network path measurement for each of a plurality of network paths at a Software-Defined Wide Area Network (SD-WAN) interface; updating a version if the network path measurement exceeds a threshold for one or more of the plurality of network paths; and selecting one of the plurality of network paths for a session based on the version according to an application policy.

Abstract: There is provided a time of flight sensor including a light source, a first pixel, a second pixel and a processor. The first pixel generates a first output signal without receiving reflected light from an external object illuminated by the light source. The second pixel generates a second output signal by receiving the reflected light from the external object illuminated by the light source. The processor calculates deviation compensation and deviation correction associated with temperature variation according to the first output signal to accordingly calibrate a distance calculated according to the second output signal.

Abstract: A screen comprises the following layers sequentially stacked from an incident side of projected light rays: a micro-lens layer, a transparent matrix layer, a total internal reflection layer, and a light-absorbing layer. The light-absorbing layer absorbs light passing through the micro-lens layer, the transparent matrix layer, and the total internal reflection layer. The micro-lens layer comprises a plurality of micro-lens units. The total internal reflection layer comprises a plurality of microstructure units. The microstructure unit has a lower first flat surface and an upper second flat surface. The first flat surface intersects the second flat surface. The plurality of microstructure units forms a serrated structure. The micro-lens units and the microstructure units are at least partially arranged in an alternating manner. The projected light rays converged toward the first flat surface exit after being totally internally reflected by the first flat surface and the second flat surface sequentially.

Abstract: A screen splicing structure is provided. The screen splicing structure includes a substrate layer, a middle adhesive layer, and a surface layer. The substrate layer includes a first substrate and a second substrate. The second substrate is spliced with the first substrate, and a seam is formed at a splicing place. The surface layer and the middle adhesive layer are stacked. The surface layer covers the seam by bonding the middle adhesive layer and the substrate layer. The peeling strength of the surface layer and the substrate layer is greater than or equal to 1,000 gf/inch. A method for forming the screen splicing structure is also provided.

Abstract: Provided are a salt form of an estrogen receptor down-regulator, a crystalline form thereof, and a preparation method therefor.

Abstract: Disclosed a method of preparing composite particles comprising a non-porous spherical particulate inorganic material deposited on a plate-like inorganic material, where refractive index of said particulate inorganic material is greater than that of said plate-like inorganic particulate material, wherein, said spherical material occupies 20 to 80% of total surface area of said plate-like material and wherein the amount of said spherical material accounts for 2 to 20 wt % of said composite particles, further wherein said plate-like inorganic material is mica and said non-porous spherical particulate inorganic material is silicone dioxide, said method comprising the steps of: (iv) silanization of said plate-like inorganic material to get a silanized material having functional groups “A”; (v) silanization of said non-porous spherical particulate inorganic material to get a silanized material having functional groups “B”, where A?B; and where said “A” and said “B” are capable of reacting with each other such that

Abstract: Systems and methods for synchronizing data between an online data source and a client application. The method includes, in response to a change in a permission associated with a user to a protected data set included in a shared data space of the online data source, receiving, with the client application associated with the user, a protected data synchronization token issued by the online data source associated with the protected data set and downloading, with the client application, the protected data set included in the shared data space from the online data source to the client application using the protected data synchronization token without re-downloading a public data set included in the shared data space. After downloading the protected data set, the method includes synchronizing the shared data space, including the protected data set and the public data set, using a stored data space synchronization token.

Abstract: A security tag including: a housing and circuitry which detects a locked state, the circuitry configured to execute a signal transfer function responsive to interchanging a pin and a lanyard in the circuitry, and/or the housing including a replaceable battery compartment locked by inserting either the pin or the lanyard into a lock mechanism which differently secures the pin and the lanyard; and an alarm, in communication with the circuitry, triggered by an undisarmed breach of the locked state.

Abstract: A total internal reflection screen includes a light diffusion layer, a total internal reflection layer and a light absorption layer arranged sequentially from an incidence side of a projected light. The light absorption layer absorbs an incident light and the light diffusion layer increases a divergence angle of an emergent light. The total internal reflection layer includes a plurality of microstructure units that is rotationally symmetrical and extends continuously in a plane of the total internal reflection screen. Each of the microstructure units includes a first material layer disposed at the side of the light diffusion layer and a second material layer disposed at the side of the light absorption layer. The interface between the first material layer and the second material layer is includes two intersecting planes, which are disposed in such a way that the projected light is totally internally reflected continuously at the two intersecting planes.

Abstract: A graphical structure model trained with labeled samples is obtained. The graphical structure model is defined based on an account relationship network that comprises a plurality of nodes and edges. The edges correspond to relationships between adjacent nodes. Each labeled sample comprises a label indicating whether a corresponding node is an abnormal node. The graphical structure model is configured to iteratively calculate, for at least one node of the plurality of nodes, an embedding vector in a hidden feature space based on an original feature of the least one node and/or a feature of an edge associated with the at least one node. A first embedding vector that corresponds to a to-be-tested sample is calculated using the graphical structure model. Abnormal account prevention and control is performed on the to-be-tested sample based on the first embedding vector.

Abstract: An LED display screen, comprising: an LED array, consisting of multiple LED light-emitting units and used for emitting a light; an optical diffusion film, provided at a light exit side of the LED array; a matrix shading frame, comprising multiple hollow shading gratings, the hollow shading gratings corresponding one-to-one to the LED light-emitting units; and a substrate, used for supporting the LED array and the matrix shading frame, where the light emitted by the LED light-emitting units, after running through the hollow shading gratings, is diffused to a viewer side via the optical diffusion film, and the LED light-emitting units emit the light towards the hollow shading gratings. The LED display screen prevents external ambient lights from being shone to optical surfaces of the LED light-emitting units and being reflected thereby, thus increasing the contrast of the LED display screen.