Abstract: The disclosure provides a controller, a method for adjusting packet flow rule, and a network communication system. The method includes: receiving, by a controller, a health status of a first port and a health status of a second port of each of a plurality of hosts in the network communication system; adjusting a packet flow rule of each of the hosts based on the health status of the first port and the health status of the second port of each of the hosts; and transmitting the adjusted packet flow rule of each of the hosts to each of the corresponding hosts to control each of the hosts to transceive a packet according to the corresponding packet flow rule.

Abstract: Barcode reading devices for creating an easy-to-use experience are provided. In one implementation, a barcode reading apparatus comprises a housing having at least a scan body and an image sensor disposed within the housing. The image sensor is configured to read the barcode. The apparatus further includes a scanning frame and a viewing frame. The scanning frame is formed in a first bottom surface of the scan body and is configured to enable the image sensor to visually detect the barcode when the barcode is placed in a scanning zone at least partially below the scan body. The viewing frame is formed in a first top surface of the scan body and is configured to enable a user to view the barcode through both the viewing frame and scanning frame when the barcode is placed in the scanning zone.

Abstract: An FPGA-based square-wave generator and a square-wave generation method.

Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

Abstract: Compositions and methods for improving plant growth are provided herein. Compositions comprise promoter sequences that direct expression of an operably linked nucleotide in a developmentally regulated manner. Polynucleotides, polypeptides, and expression constructs for expressing genes of interest whose expression may improve agronomic properties including but not limited to crop yield, biotic and abiotic stress tolerance, and early vigor, plants comprising the polynucleotides, polypeptides, and expression constructs, and methods of producing transgenic plants are also provided.

Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

Abstract: Disclosed is a personal care composition comprising turbostratic boron nitride, porous silica having a specific surface area of higher than 300 m2/g, and a cosmetically acceptable carrier.

Abstract: The present application discloses an exhaust gas after-treatment mixing device including a first plate, a second plate and a mixer. The mixer includes a first space, a second space and a third space located between the first space and the second space. Top portions of the first space and the second space are in communication with the third space. The mixer includes a first raised portion protruding into the third space and a second raised portion located below the first raised portion. A fourth space is formed between the first raised portion and the second raised portion. As a result, the distance and time of urea evaporation is increased and the mixing uniformity is improved. Besides, a package with the exhaust gas after-treatment mixing device is also provided.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The semiconductor device includes the substrate, the connection structure, the first IMD layer, the MTJ structure, and the second IMD layer. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Abstract: An optical interferometer includes a beam splitter module and an optical sensor. The beam splitter module includes a lens assembly and a splitter cube. A light incident surface of the splitter cube is substantially orthogonal to an optical axis of the lens assembly. An acute angle is between the light incident surface and a light splitting surface of the splitter cube. A sampling surface of the splitter cube is substantially parallel to the light incident surface. A light reflecting surface of the splitter cube is substantially orthogonal to the light incident surface. The light incident surface is closer to the lens assembly than the sampling surface. A reference arm is defined between a splitter position on the light splitting surface and the light reflecting surface, a sample arm is defined between the splitter position and the sampling surface, and the reference arm is longer than the sample arm.

Abstract: One or more implementations of the present specification provide risk control of transactions based on a graphical structure model. A graphical structure model trained by using labeled samples is obtained. The graphical structure model is defined based on a transaction data network that includes nodes representing entities in a transaction and edges representing relationships between the entities. Each labeled sample includes a label indicating whether a node corresponding to the labeled sample is a risky transaction node. The graphical structure model is configured to iteratively calculate an embedding vector of the node in a latent feature space based on an original feature of the node or a feature of an edge associated with the node. An embedding vector of an input sample is calculated by using the graphical structure model. Transaction risk control is performed on the input sample based on the embedding vector.

Abstract: A graphical structure model trained with labeled samples is obtained. The graphical structure model is defined based on an account relationship network that comprises a plurality of nodes and edges. The edges correspond to relationships between adjacent nodes. Each labeled sample comprises a label indicating whether a corresponding node is an abnormal node. The graphical structure model is configured to iteratively calculate, for at least one node of the plurality of nodes, an embedding vector in a hidden feature space based on an original feature of the least one node and/or a feature of an edge associated with the at least one node. A first embedding vector that corresponds to a to-be-tested sample is calculated using the graphical structure model. Abnormal account prevention and control is performed on the to-be-tested sample based on the first embedding vector.

Abstract: A graphical structure model trained by using labeled samples is obtained. The graphical structure model is defined based on an enterprise relationship network that includes nodes and edges. Each labeled sample includes a label indicating whether a corresponding node is a risky credit node. The graphical structure model is configured to iteratively calculate an embedding vector of at least one node in a hidden feature space based on an original feature of the at least one node and/or a feature of an edge associated with the at least one node. An embedding vector corresponding to a test-sample is calculated by using the graphical structure model. Credit risk analysis is performed on the test-sample. The credit risk analysis is performed based on a feature of the test-sample represented in the embedding vector. A node corresponding to the test-sample is labeled as a credit risk node.

Abstract: A semiconductor device includes a substrate, an isolation structure, and a gate structure. The substrate has an active area. The isolation structure surrounds the active area of the substrate. The gate structure is across the active area of the substrate. The isolation structure has a first portion under the gate structure and a second portion adjacent to the gate structure. A top surface of the first portion of the isolation structure is lower than a top surface of the second portion of the isolation structure.

Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.

Abstract: The antenna includes: a reflective member including a flat part; a first antenna element disposed on the flat part of the reflective member, the first antenna element being configured to transmit and receive radio waves of a first polarization; a second antenna element disposed on the flat part of the reflective member, one end of the second antenna element being located close to one end of the first antenna element, the second antenna element being configured to transmit and receive radio waves of a second polarization different from the first polarization; and a conductive member disposed close to the one ends of the first antenna element and the second antenna element and near a point of intersection where the first antenna element and the second antenna element meet when extended.

Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

Abstract: A projection apparatus and its operation method are provided. The projection apparatus includes a light-emitting device, a driving circuit coupled to the light-emitting device, and a control circuit receiving at least one video frame and analyzing color content of the at least one video frame. According to at least one control signal, the driving circuit drives the light-emitting device to generate a projected beam. The control circuit selects a highlight mode or a normal mode as a selected mode according to the color content and correspondingly sets at least one control signal to the driving circuit according to the selected mode. A brightness of the projected beam of the light-emitting device in the highlight mode is greater than that in the normal mode.