Patents by Inventor Lin Yu

Lin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8982992
    Abstract: Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data samples can comprise an expanded block having at least one cursor block. For example, at least two pre-cursor blocks and one post-cursor block can be employed. The peaks can be cancelled, for example, only in the block of data samples and in a first of the pre-cursor blocks.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 17, 2015
    Assignee: LSI Corporation
    Inventors: Kameran Azadet, Albert Molina, Joseph H. Othmer, Meng-Lin Yu, Ramon Sanchez Perez
  • Publication number: 20150062887
    Abstract: A light bar structure is provided, including a longitudinal circuit board, a plurality of light-emitting elements, and a power-input terminal. The circuit board includes a first segment, a second segment, and a third segment arranged along a longitudinal axis of the circuit board, wherein the second segment is between the first segment and the third segment. The light-emitting elements are disposed on the circuit board. The power-input terminal is disposed on the second segment and electrically connected to the light-emitting elements in parallel.
    Type: Application
    Filed: March 7, 2014
    Publication date: March 5, 2015
    Applicant: LEXTAR ELECTRONICS CORPORATION
    Inventors: Chin-Chang HSU, Chang-Lin YU
  • Patent number: 8946742
    Abstract: The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: February 3, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yung-Chi Lin, Chia-Lin Yu, Jui-Pin Hung, Chien Ling Hwang
  • Publication number: 20140364776
    Abstract: An ultrasound energy barrier for avoiding energy accumulation in a to-be-protected region during tumor treatment has a barrier element and a positioning element. The barrier element is attached to a body surface of an animal outside a to-be-protected region and a to-be-treated tumor in turn, the barrier element has an outline matched with the to-be-protected region to thus shield the to-be-protected region, so as to avoid energy accumulation in the to-be-protected region during an ultrasound focusing treatment of the to-be-treated tumor. The positioning element positioning the barrier element on the body surface during the ultrasound focusing treatment.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 11, 2014
    Inventors: Jia-yush Yen, Yu-tin Chao, Ya-lin Yu, Che-jung Hsu, Yung-yaw Chen, Ming-chih Ho
  • Patent number: 8891515
    Abstract: A method for node communication for use in a rack system is provided. The method includes providing a detecting unit for connecting to the nodes via a circuit switching device; predefining a linked list in which a limit of times for the detecting unit to communicate with each of the nodes is set; sequentially selecting one node of the nodes so that the detecting unit is connected to the one node via the circuit switching device; adding an assigned communication parameter between the detecting unit and the one node selected to the linked list, wherein a number of times of communication corresponding to the assigned communication parameter is not greater than the limit of times; and performing communication between the detecting unit and the one node selected in accordance with the assigned communication parameter in the linked list.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: November 18, 2014
    Assignee: Inventec Corporation
    Inventor: Lin Yu
  • Patent number: 8878252
    Abstract: A structure comprises a substrate, a mask, a buffer/nucleation layer, and a group III-V compound semiconductor material. The substrate has a top surface and has a recess from the top surface. The recess includes a sidewall. The first mask is the top surface of the substrate. The buffer/nucleation layer is along the sidewall, and has a different material composition than a material composition of the sidewall. The III-V compound semiconductor material continuously extends from inside the recess on the buffer/nucleation layer to over the first mask.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lin Yu, Chen-Hua Yu, Ding-Yuan Chen, Wen-Chih Chiou
  • Publication number: 20140317163
    Abstract: A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.
    Type: Application
    Filed: January 30, 2014
    Publication date: October 23, 2014
    Applicant: LSI Corporation
    Inventors: Kameran Azadet, Joseph Williams, Meng-Lin Yu
  • Patent number: 8842665
    Abstract: A method of applying an order N fast Hadamard transform (FHT) of a vector U using a mixed radix FHT in a receiver of a communication system, the N a positive integer, when receiving signals from a transmitter over a channel and generating the vector U. The method includes, in an FHT module of a decoder in the receiver, planning n stages of the mixed radix FHT, where the n is a positive integer, each stage defined by corresponding logic, decomposing the order N FHT into n low order FHTs, such that N=KnKn?1 . . . K1 and U=UKnKn?1 . . . K1, where the K is a positive integer, calculating, via the corresponding logic, each low order FHT at each stage, wherein input vectors of a subsequent stage are calculated in a proceeding stage, and reconstructing, by the decoder, calculated results of the each low order FHT to form an output vector output the decoder.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: September 23, 2014
    Assignee: LSI Corporation
    Inventors: Chengzhou Li, Meng-Lin Yu
  • Publication number: 20140235001
    Abstract: A system and method for manufacturing a light-generating device is described. A preferred embodiment comprises a plurality of LEDs formed on a substrate. Each LED preferably has spacers along the sidewalls of the LED, and a reflective surface is formed on the substrate between the LEDs. The reflective surface is preferably located lower than the active layer of the individual LEDs.
    Type: Application
    Filed: May 2, 2014
    Publication date: August 21, 2014
    Inventors: Ding-Yuan Chen, Chia-Lin Yu, Chen-Hua Yu, Wen-Chih Chiou
  • Patent number: 8809300
    Abstract: Disclosed is a depolymerized glycosaminoglycan from Thelenota ananas (dTHG), weight average molecular weight of which is about 8000˜20000 Da, and monosaccharide components of which are acetylgalactosamine (GalNAc), glucuronic acid (GlcUA), fucose (Fuc) or their sulfates (expressed as —OSO3?), in which molar ratio of GalNAc:GlcUA:Fuc:—OSO3? is about 1:(1±0.3):(1±0.3):(3.5±0.5). Said dTHG is a potent endogenous inhibitor of factor X, which has good anticoagulant and antithrombotic activity, and can be used for the prevention and/or treatment of thrombotic diseases. Also provided is a method for preparing said dTHG, which comprises steps of 1) extracting and obtaining fucosylated glycosaminoglycan (THG) from the body wall of Thelenota ananas; 2) depolymerizing THG to obtain dTHG by method of peroxide depolymerization or method of peroxide depolymerization catalyzed by catalyst of the fourth period transition metal ions; 3) removing impurities with lower and/or higher molecular weight in dTHG.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: August 19, 2014
    Assignee: Shenzhen Neptunus Pharmaceutical Co., Ltd.
    Inventors: Jinhua Zhao, Hui Kang, Mingyi Wu, Weizhen Zeng, Zi Li, Yuan Gao, Jing Cui, Zhiguo Wang, Hanlin Feng, Lin Yu
  • Patent number: 8804672
    Abstract: In one embodiment, the invention is a method for performing preamble detection in a wireless communication network. The method performs a first dwell, wherein non-overlapping chunks of received data are processed to generate partial correlation values for each possible combination of a signature code and delay. Candidate selection is performed by comparing each of the partial correlation values to a candidate-selection threshold. For each detected candidate, the chunks of received data are processed to generate full correlation values. Each full correlation value is then compared to a preamble-detection threshold to detect a transmitted signature. Generating full correlation values for only the selected candidates reduces the computation complexity over prior-art methods that generate full correlation values for all signatures at all delays.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: August 12, 2014
    Assignee: LSI Corporation
    Inventors: Ivan L. Mazurenko, Alexander A. Petyushko, Meng-Lin Yu, Jian-Guo Chen
  • Patent number: 8803189
    Abstract: A circuit structure includes a substrate; a patterned mask layer over the substrate, wherein the patterned mask layer includes a plurality of gaps; and a group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layer includes a first portion over the mask layer and second portions in the gaps, wherein the III-V compound semiconductor layer overlies a buffer/nucleation layer.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chia-Lin Yu, Ding-Yuan Chen, Wen-Chih Chiou, Hung-Ta Lin
  • Publication number: 20140203796
    Abstract: A silicon device, e.g., a nanoelectromechanical resonator, has a silicon substrate; an oxide layer having a trench therein; a silicon device layer over the oxide layer; and a nanowire disposed at least partly over the trench. Substantially no oxide or polysilicon is over the nanowire in the trench. A polyimide layer over the silicon device layer includes an opening over the trench. A silicon device can include silicon-on-insulator layers and at least one complementary metal-oxide semiconductor transistor in addition to a nanowire substantially suspended over a trench. A system for measurement of a nanoresonator includes an AC source in series with the nanoresonator to provide an electrical signal thereto at a selected first frequency. Electrode(s) adjacent to and spaced apart from the nanoresonator are driven by voltage source. A detector detects a current through the nanoresonator.
    Type: Application
    Filed: August 16, 2013
    Publication date: July 24, 2014
    Applicant: Purdue Research Foundation
    Inventors: Saeed Mohammadi, Hossein Pajouhi, Jeffrey Frederick Rhoads, Lin Yu
  • Patent number: 8779445
    Abstract: A light emitting diodes (LEDs) is presented. The LED includes a stress-alleviation layer on a substrate. Open regions and stress-alleviation layer regions are formed on the substrate. Epitaxial layers are disposed on the substrate, at least in the open regions therein, thereby forming an LED structure. The substrate is diced through at least a first portion of the stress-alleviation regions, thereby forming the plurality of LEDs.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Ta Lin, Ding-Yuan Chen, Wen-Chih Chiou, Chia-Lin Yu
  • Publication number: 20140185239
    Abstract: An electronic device includes a chassis, an air-guiding housing mounted in the chassis, and an airflow control member. The chassis includes a base panel with a plurality of ventilation holes. The air-guiding housing comprises an airflow passage aligned with the plurality of ventilation holes. The airflow control member includes a shielding plate attached on the base panel. The airflow control member is movable between a first position and a second position. In the first position, the shielding plate is located beside the air-guiding housing, and the airflow passage is communicated with the plurality of ventilation holes for allowing air flowing to an outside of the chassis via the plurality of ventilation holes. In the second position, the shielding plate is located between the air-guiding housing and the base panel for closing the plurality of ventilation holes and preventing air flowing to the outside of the chassis.
    Type: Application
    Filed: August 30, 2013
    Publication date: July 3, 2014
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (WUHAN) CO., LTD.
    Inventors: LIN YU, ZHI-PING WU
  • Publication number: 20140179215
    Abstract: An electronic device enclosure includes a cabinet, an air guiding duct, and a controlling member. The cabinet includes a bottom plate with a heat dissipating area. The air guiding duct defines an ventilation hole and includes a side panel. An air outlet is defined in the side panel and communicates with the ventilation hole. The controlling member includes a shielding panel attached to the bottom plate and a shielding door connected to the shielding panel. The controlling member is rotatable relative to the bottom plate between in a first position and a second position. In the first position, the shielding door abuts the side panel to cover the air outlet, and the ventilation hole communicates with the heat dissipating area. In the second position, the shielding panel covers the ventilation hole, and the shielding door is disengaged from the side panel.
    Type: Application
    Filed: August 2, 2013
    Publication date: June 26, 2014
    Applicants: Hon Hai Precision Industry Co., Ltd., Hong Fu Jin Precision Industry (WuHan) Co., Ltd.
    Inventors: Lin Yu, Zhi-Ping Wu
  • Publication number: 20140166979
    Abstract: A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu, Hung-Ta Lin
  • Publication number: 20140159208
    Abstract: A structure comprises a substrate, a mask, a buffer/nucleation layer, and a group III-V compound semiconductor material. The substrate has a top surface and has a recess from the top surface. The recess includes a sidewall. The first mask is the top surface of the substrate. The buffer/nucleation layer is along the sidewall, and has a different material composition than a material composition of the sidewall. The III-V compound semiconductor material continuously extends from inside the recess on the buffer/nucleation layer to over the first mask.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 12, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lin Yu, Chen-Hua Yu, Ding-Yuan Chen, Wen-Chih Chiou
  • Patent number: 8716723
    Abstract: A system and method for manufacturing a light-generating device is described. A preferred embodiment comprises a plurality of LEDs formed on a substrate. Each LED preferably has spacers along the sidewalls of the LED, and a reflective surface is formed on the substrate between the LEDs. The reflective surface is preferably located lower than the active layer of the individual LEDs.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: May 6, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Ding-Yuan Chen, Chia-Lin Yu, Chen-Hua Yu, Wen-Chih Chiou
  • Patent number: 8719323
    Abstract: A method for efficient state transition matrix based LFSR computations are disclosed. A polynomial associated with a linear feedback shift register is defined. This polynomial is used to generate a single step state transition matrix. The single step state transition matrix is then modified into a more general k-step state transition matrix. The resultant combined matrix is reduced in size and can be multiplied by a state input vector, ultimately producing a plurality of next state-input vectors thereby providing improved efficiency in computing a LFSR.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: May 6, 2014
    Assignee: LSI Corporation
    Inventor: Meng-Lin Yu