Patents by Inventor Lung Huang

Lung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11482470
    Abstract: An electronic package is provided and includes an electronic element, an intermediary structure disposed on the electronic element, and a heat dissipation element bonded to the electronic element through the intermediary structure. The intermediary structure has a flow guide portion and a permanent fluid combined with the flow guide portion so as to be in contact with the electronic element, thereby achieving a preferred heat dissipation effect and preventing excessive warping of the electronic element or the heat dissipation element due to stress concentration.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: October 25, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Publication number: 20220336323
    Abstract: An electronic package is provided and includes an electronic element, an intermediary structure disposed on the electronic element, and a heat dissipation element bonded to the electronic element through the intermediary structure. The intermediary structure has a flow guide portion and a permanent fluid combined with the flow guide portion so as to be in contact with the electronic element, thereby achieving a preferred heat dissipation effect and preventing excessive warping of the electronic element or the heat dissipation element due to stress concentration.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Publication number: 20220320148
    Abstract: A preparation method of an LCoS panel provides a wafer substrate at a wafer level, the substrate including die areas with active circuits. A seal is formed on the wafer substrate, coupling to a transparent substrate. Vias extend through a thick silicon substrate and there are conductive interfaces on the second surface in each die area, the active circuit being connected to the back side of the wafer substrate by the vias and the conductive interfaces. The wafer substrate and the transparent substrate are cut to obtain LCoS panels. These processes (especially the circuit packaging) are all performed at wafer level, improving production efficiency and reducing production cost. An LCoS panel so prepared is also disclosed.
    Type: Application
    Filed: February 15, 2022
    Publication date: October 6, 2022
    Inventors: KUO-LUNG HUANG, RONG HSU
  • Publication number: 20220293484
    Abstract: An integrated circuit package system includes a substrate, a plurality of leads, N semiconductor devices, N first heat sinks, an encapsulating body, a second heat sink and a plurality of heat-dissipating fins protruding upward from the second heat sink, where N is a natural number. The leads are formed on a lower surface of the substrate. Each of the semiconductor devices is attached on an upper surface of the substrate, and includes a plurality of bonding pads which each is electrically connected to the corresponding lead. Each first heat sink is thermally coupled to a first top surface of the corresponding semiconductor device. The encapsulating body is formed to cover the substrate, the N semiconductor devices and the N first heat sinks such that the leads are exposed. The second heat sink is mounted on the encapsulating body, and is thermally coupled to the N first heat sinks.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 15, 2022
    Inventors: Chun-Lung HUANG, Chih-Ming CHEN
  • Publication number: 20220282858
    Abstract: An illumination device selectively disposed on an object having a first side and a second side is provided. The illumination device comprises a light-emitting module, a camera unit and a rotation mechanism. The lighting direction of the light-emitting module points towards the front of the first side. The central filming direction of the camera unit points towards the front of the first side. The light-emitting module is coupled to the rotation mechanism such that the light-emitting module is capable of rotating about an axis of the rotation mechanism. When the lighting direction falls in a first angular range relative to the axis of the rotation mechanism, the light-emitting module provides a first mode illumination. When the lighting direction falls in a second angular range relative to the axis of the rotation mechanism, the light-emitting module provides a second mode illumination. Said first angular range is different from said second angular range.
    Type: Application
    Filed: January 19, 2022
    Publication date: September 8, 2022
    Applicant: Qisda Corporation
    Inventor: Chih-Lung HUANG
  • Patent number: 11430750
    Abstract: A semiconductor device package includes a first substrate, an antenna, a support layer, a dielectric layer and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The antenna element is disposed on the second surface of the first substrate. The support layer is disposed on the first surface of the first substrate and at the periphery of the first surface of the first substrate. The support layer has a first surface facing away from the first substrate. The dielectric layer is disposed on the first surface of the support layer and spaced apart from the first substrate. The dielectric layer is chemically bonded to the support layer. The second substrate is disposed on a first surface of the dielectric layer facing away from the support layer.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: August 30, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Min Lung Huang, Yuh-Shan Su
  • Patent number: 11428946
    Abstract: According to various embodiments, a collimator includes a substrate defining a plurality of channels through the substrate. The substrate includes a first surface and a second surface opposite the first surface. Each of the channels includes a first aperture exposed from the first surface, a second aperture between the first surface and the second surface, and a third aperture exposed from the second surface. The first aperture and the third aperture are larger than the second aperture.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: August 30, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Feng Chiang, Tsung-Tang Tsai, Min Lung Huang
  • Patent number: 11431181
    Abstract: A wireless sound output device includes a wireless earbud and a charging base. The wireless earbud is placed in the charging base. If a true wireless stereo Bluetooth controller of the wireless earbud detects that a mode switching circuit of the charging base is switched to a wireless Bluetooth receiver mode, an analog signal is transmitted to an audio source output hole of the charging base through an audio source analog signal output switching unit of the wireless earbud.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: August 30, 2022
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Pao-Chung Chao, Pei-Ming Chang, Shih-Chieh Hsu, Wei-Lung Huang
  • Publication number: 20220268991
    Abstract: A single-mode crystal fiber is provided. The fiber has a core. The core is made of a crystalline material with a melting point above 1900 degrees Celsius (° C.). The core has a coat. The coat is made of a crystalline material the same as that of the core. Through immersion plating under a low vacuum pressure and a high temperature, the material of the coat is sintered to form an outer layer covering the core. Thus, the thickness of the coat is controlled. A single crystal totally the same as that of the core is grown in a solid state with no ceramics contained. Consequently, the crystal contains no ceramics; and, through being sintered in a vacuum environment, the crystal has pores the smallest in size and the fewest in number, as compared to those sintered under a normal pressure.
    Type: Application
    Filed: March 22, 2021
    Publication date: August 25, 2022
    Inventors: Teng-I Yang, Yu-Chan Lin, Sheng-Lung Huang
  • Patent number: 11424212
    Abstract: A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 23, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Wei Chang, Shang-Wei Yeh, Chung-Hsi Wu, Min Lung Huang
  • Patent number: 11410954
    Abstract: Provided is an electronic package, including a first substrate of a first conductive structure and a second substrate of a second conductive structure, where a first conductive layer, a bump body and a metal auxiliary layer of the first conductive structure are sequentially formed on the first substrate, and a metal pillar, a second conductive layer, a metal layer and a solder layer of the second conductive structure are sequentially formed on the second substrate, such that the solder layer is combined with the bump body and the metal auxiliary layer to stack the first substrate and the second substrate.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: August 9, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Patent number: 11411073
    Abstract: A semiconductor package device includes a first conductive wall, a second conductive wall, a first insulation wall, a dielectric layer, a first electrode, and a second electrode. The first insulation wall is disposed between the first and second conductive walls. The dielectric layer has a first portion covering a bottom surface of the first conductive wall, a bottom surface of the second conductive wall and a bottom surface of the first insulation wall. The first electrode is electrically connected to the first conductive wall. The second electrode is electrically connected to the second conductive wall.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 9, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao Hsuan Chuang, Huang-Hsien Chang, Min Lung Huang
  • Patent number: 11401159
    Abstract: A MEMS transducing apparatus includes a substrate, a conductive pad, a stacked structure of a transducing device, a first polymer layer, a second polymer layer and a third polymer layer. An upper cavity is formed through the substrate. The conductive pad is formed on a first surface of the substrate to cover a first opening of the upper cavity. The stacked structure of the transducing device is formed on the conductive pad. The first polymer layer is formed on the first surface of the substrate. A lower cavity is formed through the first polymer layer. The stacked structure of the transducing device is exposed within the lower cavity. The third polymer layer is formed on a second surface of the substrate to cover a second opening of the upper cavity. The second polymer layer is formed on the first polymer layer to cover a third opening of the lower cavity.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: August 2, 2022
    Assignee: FORMOSA MATERIAL INDUSTRIAL CORP.
    Inventors: Chun-Lung Huang, Ying-Hsiang Chen, Fu-Hsuan Yang
  • Patent number: 11401391
    Abstract: An oyster paper and a manufacturing method thereof are provided. The oyster paper is made of 60%-70% oyster shell powder, 10%-20% polymer, 15%-17% natural biodegradation inducing agent, and 3%-5% natural biodegradation assisting additive agent, by volume ratio, which are subjected to mixing and pre-melting processing, followed by compounding and pelletizing to prepare oyster paper pellets, which are then subjected to film blowing processing to be film-blown into an oyster paper product having a thickness of 0.05-0.5 millimeters. The oyster paper possesses the quality of wood pulp paper and shows bettered stiffness and wider applications. The oyster paper also provides, after being disposed and buried, an effect of being 100% natural degradation into compost for fertilizing the soil. As such, a kind of oyster paper featuring recycling and reuse of oceanic creature waste shell and natural microorganism induced degradation for composting and recycling and a manufacturing method thereof are provided.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: August 2, 2022
    Assignee: Don Jia Poly Plastic Ltd.
    Inventors: Jui Lung Huang, Chin Chih Huang
  • Publication number: 20220229337
    Abstract: An LCoS panel and a method of preparation includes wafer level packaging, manufacturing vias through a silicon substrate in each die area of a wafer substrate, and manufacturing conductive interfaces on a back surface of the wafer substrate. Each conductive interface corresponds to one via and so connected to an active circuit of the die area where the conductive interface is located. Liquid crystal packaging is applied, a seal coated to surround the pixel circuit area of the active circuit on a front surface of the wafer substrate, injecting liquid crystal into a space defined by the seal, the seal coupling glass substrate comprising a transparent conductive layer and the wafer substrate, and then cutting. Wafer level chip scale packaging of the LCoS panels is thus achieved, the cost is reduced, the obtained LCoS panels are small in total area and of greater thinness.
    Type: Application
    Filed: January 21, 2022
    Publication date: July 21, 2022
    Inventors: YEUK-KEUNG FUNG, KUO-LUNG HUANG
  • Patent number: 11393983
    Abstract: The present disclosure provides phenyl biphenylpyrimidine compounds of formula (I) and an organic electroluminescent device using the same: wherein X1 and A1 each independently represents substituted or unsubstituted C6-30 aryl or substituted or unsubstituted C5-30 heteroaryl having at least one heteroatom selected from the group consisting of N, O, and S, and n represents an integer of 1 or 2.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 19, 2022
    Assignee: E-RAY OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Heh-Lung Huang, Teng-Chih Chao, Po-Wei Hsu, Yi-Huan Fu, Chi-Jen Lin
  • Patent number: 11373956
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first semiconductor device, a first conductive layer and a second conductive layer. The first semiconductor device has a first conductive pad. The first conductive layer is disposed in direct contact with the first conductive pad. The first conductive layer extends along a direction substantially parallel to a surface of the first conductive pad. The second conductive layer is disposed in direct contact with the first conductive pad and spaced apart from the first conductive layer.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: June 28, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Min Lung Huang, Hung-Jung Tu, Hsin Hsiang Wang, Chih-Wei Huang, Shiuan-Yu Lin
  • Publication number: 20220196216
    Abstract: A clamping lamp for clamping a monitor comprises a first light source and a clamping body including a second light source, a first clamping component including a first clamping portion and a lamp connection portion, and a second clamping component including a second clamping portion. The lamp connection portion connects with the first clamping portion and the first light source. The first clamping portion leans against a front surface of the monitor and the second clamping portion leans against a back surface of the monitor when the clamping lamp clamps the monitor so the first light source is located above a top surface of the monitor. The first light source emits light toward a first zone that the front surface faces toward. The second light source emits light toward a second zone that the back surface faces toward.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 23, 2022
    Applicant: Qisda Corporation
    Inventor: Chih-Lung HUANG
  • Patent number: 11359297
    Abstract: A method for electrolysis of water and a method for preparing a catalyst for electrolysis of water are provided. The method for electrolysis of water includes using a high entropy alloy as a catalyst. Further, the method for preparing a catalyst for electrolysis of water includes the steps of placing a substrate in an aqueous electrolyte containing a high entropy alloy precursor and performing an electroplating process on the substrate to form a high entropy alloy catalyst on the substrate.
    Type: Grant
    Filed: March 15, 2020
    Date of Patent: June 14, 2022
    Assignees: National Tsing Hua University, Chang Chun Plastics Co., Ltd., Chang Chun Petrochemical Co., Ltd., DAIREN CHEMICAL CORP.
    Inventors: Chun-Lung Huang, Shih-Yuan Lu
  • Patent number: 11355426
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are substantially arranged in a row and spaced apart from one another. The conductive through via extends through the dam portions.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: June 7, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Min Lung Huang