Patents by Inventor Manish

Manish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050174828
    Abstract: A magnetic random access memory (MRAM) that includes an array of magnetic memory cells and a plurality of word and bit lines connecting columns and rows of the memory cells so that the memory cells are positioned at cross-points of the word and bit lines. Each memory cell has a magnetic reference layer and a magnetic data layer. Each magnetic reference layer and each magnetic data layer has a magnetization that is switchable between two states under the influence of a magnetic field and each reference layer has at a first temperature a coercivity that is lower than that of each data layer at the first temperature. The MRAM also includes a plurality of heating elements each proximate to a respective data layer. Each heating element provides in use for localized heating of the respective data layer to reduce the coercivity of the data layer so as to facilitate switching of the data layer.
    Type: Application
    Filed: February 11, 2004
    Publication date: August 11, 2005
    Inventor: Manish Sharma
  • Publication number: 20050176206
    Abstract: An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil depositing a dielectric material, planarizing the dielectric material thereby exposing a portion of the at least one material and depositing a conductor material in contact with the exposed portion of the at least one material.
    Type: Application
    Filed: April 13, 2005
    Publication date: August 11, 2005
    Inventors: Manish Sharma, Thomas Anthony, Heon Lee
  • Publication number: 20050166975
    Abstract: A latching microregulator for regulating liquid flow on micro-scale levels comprises a substrate having an inlet port and an outlet port, a valve element defining a valve chamber for opening and closing the inlet port, and an actuator assembly for actuating the valve element. The valve chamber is configured to contain a volume of fluid, and the inlet port and the outlet port are in fluid communication with the valve chamber to provide a liquid flow path through the chamber. The actuator assembly comprises a cantilever beam for moving the valve element between an open position and a closed position, an actuator, such as a piezoelectric element, for moving the cantilever beam, and a latch, such as a permanent magnet, for securing the cantilever beam in the closed position. A flow regulation system comprises a plurality of fluid channels of varied flow conductance and a plurality of latching microregulators for selectively blocking or allowing flow through each of the fluid channels.
    Type: Application
    Filed: April 4, 2005
    Publication date: August 4, 2005
    Applicant: Cytonome, Inc.
    Inventors: John Gilbert, Bernard Bunner, Sebastian Bohm, Manish Deshpande
  • Publication number: 20050171987
    Abstract: The present invention provides a folded low-complexity (FLC) pipeline. In one embodiment, the FLC pipeline includes a dot product unit chain configured to employ only addition and multiplication operations to compute intermediate numerators and denominators from a received signal matrix, a channel gain matrix and a noise matrix. Additionally, FLC pipeline also includes a divider stage configured to terminate the dot product unit chain by computing an unscaled quotient and a scale factor from ultimate ones of the intermediate numerators and denominators.
    Type: Application
    Filed: August 17, 2004
    Publication date: August 4, 2005
    Applicant: Texas Instruments Incorporated
    Inventors: Manish Goel, David Milliner, Srinath Hosur, Muhammad Ikram
  • Publication number: 20050169399
    Abstract: The present invention provides a signal field scaler for use with a multiple-input, multiple-output (MIMO) transmitter employing N transmit antennas, where N is at least two. In one embodiment, the signal field scaler includes a signal field generator configured to provide a signal field corresponding to a multiple concurrent transmission to each of the N transmit antennas during a time interval. Additionally, the signal field scaler also includes a signal field adapter coupled to the signal field generator and configured to apply a vector of scale factors to the signal field for each of the N transmit antennas during the time interval to allow proper decoding of the signal field by a legacy receiver and a MIMO receiver.
    Type: Application
    Filed: January 5, 2005
    Publication date: August 4, 2005
    Applicant: Texas Instruments Incorporated
    Inventors: David Magee, Michael DiRenzo, Manish Goel
  • Publication number: 20050169398
    Abstract: The present invention provides a gain training generator for use with a multiple-input, multiple-output (MIMO) transmitter employing N transmit antennas where N is at least two. In one embodiment, the gain training generator includes a fundamental training encoder configured to provide a basic gain training sequence to one of the N transmit antennas during a time interval to produce a basic gain training waveform having a basic peak-to-average ratio (PAR). Additionally, the gain training generator also includes a supplemental training encoder coupled to the fundamental training encoder and configured to further provide (N?1) supplemental gain training sequences to (N?1) remaining transmit antennas, respectively, during the time interval to produce supplemental gain training waveforms wherein each has a supplemental PAR substantially equal to the basic PAR.
    Type: Application
    Filed: January 4, 2005
    Publication date: August 4, 2005
    Applicant: Texas Instruments Incorporated
    Inventors: David Magee, Michael DiRenzo, Manish Goel
  • Publication number: 20050172306
    Abstract: Described are methods, apparatus and computer programs for determining run-time dependencies between logical components of a data processing environment. Components of the data processing environment are monitored by monitoring agents accessing run-time activity data via APIs of the managed system. A dependency generator identifies correlations between the run-time activity of the monitored components. For synchronous monitored systems, the dependency generator calculates an activity period for monitored components and determines which component's activity periods contain the activity periods of other components. Containment is used as an indicator of a likely dependency relationship, and a weighting is computed for each dependency relationship based on the consistency of containment.
    Type: Application
    Filed: October 20, 2003
    Publication date: August 4, 2005
    Inventors: Manoj Agarwal, Manish Gupta, Gautam Kar, Parviz Kermani, Anindya Neogi
  • Publication number: 20050169397
    Abstract: The present invention provides a concurrent gain generator for use with a MIMO transmitter having an N of two or more transmit antennas. In one embodiment, the concurrent gain generator includes a first sequence formatter that provides one of the N transmit antennas with a gain training sequence during an initial time interval, and a second sequence formatter that further provides (N?1) remaining transmit antennas with (N?1) additional gain training sequences during the initial time interval to train receive gains. The present invention also provides a non-concurrent gain adjuster for use with a MIMO receiver employing an M of two or more receive antennas. In one embodiment, the non-concurrent gain adjuster includes a gain combiner that computes a common receive gain as a function of M independent receive gains, and a gain applier that applies the common receive gain to receivers associated with the M receive antennas.
    Type: Application
    Filed: September 29, 2004
    Publication date: August 4, 2005
    Applicant: Texas Instruments Incorporated
    Inventors: Manish Goel, David Magee, Michael DiRenzo, Michael Polley
  • Publication number: 20050170533
    Abstract: A magnetic tunnel junction device with a compositionally modulated electrode and a method of fabricating a magnetic tunnel junction device with a compositionally modulated electrode are disclosed. An electrode in electrical communication with a data layer of the magnetic tunnel junction device includes a high resistivity region that has a higher resistivity than the electrode. As a result, a current flowing through the electrode generates joule heating in the high resistivity region and that joule heating increases a temperature of the data layer and reduces a coercivity of the data layer. Consequently, a magnitude of a switching field required to rotate an alterable orientation of magnetization of the data layer is reduced. The high resistivity region can be fabricated using a plasma oxidation, a plasma nitridation, a plasma carburization, or an alloying process.
    Type: Application
    Filed: January 30, 2004
    Publication date: August 4, 2005
    Inventors: Heon Lee, Manish Sharma
  • Publication number: 20050170831
    Abstract: A preamble frequency switching design technique for frequency switching the training symbols within the preamble associated with a MIMO communication system ensures that data throughput is optimized.
    Type: Application
    Filed: August 30, 2004
    Publication date: August 4, 2005
    Inventors: David Magee, Manish Goel, Michael DiRenzo
  • Publication number: 20050170628
    Abstract: An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil, forming a re-entrant profile with the remaining portion of the liftoff stencil and depositing a conductor material in contact with the at least one material on the re-entrant profile.
    Type: Application
    Filed: January 31, 2004
    Publication date: August 4, 2005
    Inventors: Manish Sharma, Thomas Anthony, Heon Lee
  • Patent number: 6924793
    Abstract: A computer input system is disclosed that utilizes a glove-type multiple styli device that is mapped for operation based on their finger position. The input system can further include a digitizing tablet, such as one using MRAM cells.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: August 2, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Manish Sharma
  • Patent number: 6924539
    Abstract: An exemplary nonvolatile memory array comprises a substrate and a plurality of memory cells formed on the substrate, each of the memory cells being addressable via at least first and second conductors during operations. An exemplary memory cell in the exemplary memory array includes a ferromagnetic annular data layer having an opening, the opening enabling the second conductor to electrically contact the first conductor, an intermediate layer on at least a portion of the annular data layer, and a soft reference layer on at least a portion of the intermediate layer.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: August 2, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Manish Sharma, Lung Tran
  • Publication number: 20050163041
    Abstract: A Hybrid IMMSE-LMMSE receiver processing technique predicts performance of and selects between iterative and non-iterative decoding of symbols based on an intelligent metric. Based on a pre-specified criterion, the receiver determines if a correct first-stage decision is made or not. If a correct decision is made, then it follows iterative processing like in BLAST. Alternatively, if a wrong decision is found to have occurred, the receiver resorts to LMMSE estimation processing.
    Type: Application
    Filed: January 26, 2004
    Publication date: July 28, 2005
    Inventors: Muhammad Ikram, Srinath Hosur, Michael Polley, Manish Goel
  • Publication number: 20050161715
    Abstract: A cross point resistive memory array has a first array of cells arranged generally in a plane. Each of the memory cells includes a memory storage element and is coupled to a diode. The diode junction extends transversely to the plane of the array of memory cells.
    Type: Application
    Filed: March 30, 2004
    Publication date: July 28, 2005
    Inventors: Frederick Perner, Manish Sharma
  • Patent number: 6921954
    Abstract: This invention provides an asymmetrically patterned magnetic memory storage device. In a particular embodiment at least one magnetic memory cell is provided. Each magnetic memory cell provides at least one ferromagnetic data layer of a first size, the data layer characterized by an alterable orientation of magnetization, an intermediate layer in contact with the data layer and at least one ferromagnetic reference layer of a second size, the reference layer characterized by a reference magnetic field. The reference layer is in contact with the intermediate layer, opposite from and asymmetric to the data layer. The magnetic memory cell is characterized as having only one-end involvement. More specifically, the asymmetric alignment provides that only one set of magnetic poles are in substantial vertical alignment, and as such subject to the strong influence of one another.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: July 26, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Manish Sharma
  • Patent number: 6922472
    Abstract: The present invention provides permutation instructions which can be used in software executed in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. The permute instructions are based on a Benes network comprising two butterfly networks of the same size connected back-to-back. Intermediate sequences of bits are defined that an initial sequence of bits from a source register are transformed into. Each intermediate sequence of bits is used as input to a subsequent permutation instruction. Permutation instructions are determined for permitting the initial source sequence of bits into one or more intermediate sequence of bits until a desired sequence is obtained. The intermediate sequences of bits are determined by configuration bits. The permutation instructions form a permutation instruction sequence of at least one instruction.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: July 26, 2005
    Assignee: Teleputers, LLC
    Inventors: Ruby B. Lee, Xiao Yang, Manish Vachharajani
  • Publication number: 20050158881
    Abstract: This invention provides a method of making nano-scaled toroidal magnetic memory cells, such as may be used, for example, in magnetic random access memory (MRAM). In a particular embodiment a semiconductor wafer substrate is prepared and a conductor layer is provided upon the wafer. A hard layer is deposited upon the first conductor. From the hard layer, ion etching is employed to form an annular wall about a pillar, the wall and pillar defining an annular slot. A ferromagnetic data layer is deposited within the annular slot and a junction stack is then provided upon at least a portion of the data layer. A dielectric is applied to insulate the structure and then planarized to expose the pillar.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 21, 2005
    Inventor: Manish Sharma
  • Publication number: 20050157540
    Abstract: This invention provides a soft-reference four conductor magnetic memory storage device. In a particular embodiment, there are a plurality of parallel electrically conductive first sense conductors and a plurality of parallel electrically conductive second sense conductors. The first and second sense conductors may provide a cross point array or a series connected array. Soft-reference magnetic memory cells are provided in electrical contact with and located and at each intersection. In addition there are a plurality of parallel electrically conductive write rows substantially proximate to and electrically isolated from the first sense conductors. A plurality of parallel electrically conductive write columns transverse to the write rows, substantially proximate to and electrically isolated from the second sense conductors, forming a write cross point array with a plurality of intersections, is also provided.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 21, 2005
    Inventors: Fredrick Perner, Manish Sharma
  • Publication number: 20050158380
    Abstract: The present invention relates to sustained release oral dosage forms of gabapentin and at least one rate controlling polymer, and a process for the preparation of the sustained release oral dosage forms, and a process for the preparation thereof. The sustained release tablet includes gabapentin or a pharmaceutically acceptable salt or hydrates thereof and at least one rate-controlling polymer such that the tablet provides therapeutically effective plasma levels of gabapentin for a period of up to about 12 hours.
    Type: Application
    Filed: June 6, 2003
    Publication date: July 21, 2005
    Inventors: Manish Chawla, Rajeev Raghuvanshi, Ashok Rampal