Patents by Inventor Masayuki Mizuno

Masayuki Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6078618
    Abstract: A reference picture storing section 101 stores reference picture data referred in a motion vector estimation. A current picture storing section 102 stores a current picture data for the motion vector estimation. A motion vector estimating section 103 takes matching between the current picture data and the reference picture data to estimate a motion vector having the minimum difference. A motion vector statistics processing section 104 calculates an average value and a histogram from each picture of an estimated motion vector. A shift vector setting section 105 calculates a shift vector of a motion vector search window based on the average value and histogram in each of coded pictures. A search window designating section 106 designates a motion vector to be searched according to the calculated shift vector so as to cause the motion vector estimating section 103 to estimate the motion vector.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: June 20, 2000
    Assignee: NEC Corporation
    Inventors: Yutaka Yokoyama, Shu-Yu Zhu, Masayuki Mizuno
  • Patent number: 6064498
    Abstract: This invention relates to an image forming apparatus for recording an image on recording paper. The apparatus has a main base frame internally provided with an imaging unit for recording an image on recording paper, an upper frame disposed on-the main base frame and pivotally movable about an axis of a pivot provided on one end of the upper frame corresponding to a rear side of the apparatus to open a front side of the apparatus, a document feeder unit disposed on the upper frame for feeding an original document set thereon toward the front side, a document discharge tray attached to the main base frame for receiving the document fed by the document feeder unit, and a recording paper discharge tray attached to the main base frame beneath the document discharge tray for receiving the recording paper carrying the recorded image. The document discharge tray and the recording paper discharge tray are integrally attached to the main base frame via a tray frame to form a one piece unit.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: May 16, 2000
    Assignee: Kyocera Mita Corporation
    Inventors: Susumu Taniguchi, Hideaki Kimata, Keiji Ban, Hiroyuki Arima, Masayuki Mizuno, Katsuhide Yamaguchi, Makoto Eki
  • Patent number: 6051448
    Abstract: In a method of manufacturing an electronic component for forming a conductor pattern on an insulating substrate by transfer method employing intaglio printing technique, this manufacturing method comprises a step of fabricating an intaglio 20 made of flexible resin forming an insulating layer 23 on a groove 21, a step of filling the groove 21 with Ag paste 24 and drying, a step of overlaying the intaglio 20 on an insulating substrate 2 having a water-soluble resin 28 formed on the surface by pressing a pressing portion 26, freezing, peeling off the intaglio 20 and insulating substrate 2, and transferring the pattern of the Ag paste 24, and a step of firing it and forming a conductor pattern.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: April 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaaki Hayama, Noboru Mouri, Tetsu Murakawa, Hayami Matsunaga, Masayuki Mizuno
  • Patent number: 5978930
    Abstract: A clock signal control system of the present invention includes a simple circuit for generating a clock stop signal. With this circuit, the system is small size and easy to design and consumes a minimum of power.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: November 2, 1999
    Assignee: NEC Corporation
    Inventors: Koichiro Furuta, Masayuki Mizuno, Junichi Goto
  • Patent number: 5905926
    Abstract: An image forming apparatus of this invention is constructed such that a main base frame constituting the apparatus is formed with a pair of first positioning pins. An attachment member is formed with a pair of second positioning pins and positioning holes for fittingly receiving the first positioning pins therein to position the attachment member relative to the main base frame. A brake force supplier formed with mounting holes is attached to the attachment member while positioned relative thereto by fitting insertion of the second positioning pins in the mounting holes. When the attachment member is not used, another brake force supplier can be directly mounted on the main base frame and positioned relative thereto by fitting insertion of the first positioning pins in mounting holes of the brake force supplier.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: May 18, 1999
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Susumu Taniguchi, Hideaki Kimata, Hiroyuki Arima, Keiji Ban, Masayuki Mizuno, Katsuhide Yamaguchi, Makoto Eki
  • Patent number: 5889928
    Abstract: Method of automating at least a portion of an output gradation adjustment job for an image output apparatus. Test image data are corrected according to an initial gradation correction curve, and a test image is formed according to the image data thus corrected. The test image is read by a scanner to obtain read data. Based on the read data thus obtained, test image data are newly formed. Based on the newly formed test image data, a test image is again formed. The second-time test image thus formed is read by the scanner to obtain read data. Based on the read data obtained by reading the second-time test image, the initial gradation correction curve and a predetermined reference output curve, candidate point data are obtained. Based on the candidate point data, a gradation correction curve is formed and set.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: March 30, 1999
    Assignee: MITA Industrial Co., Ltd.
    Inventors: Koji Nakamura, Masayuki Mizuno, Ryuichi Okumura
  • Patent number: 5860044
    Abstract: This invention relates to an image forming apparatus constructed such that an upper frame is openably mounted on a main base frame and a pivotal movement transmitter (gear) is rotatably mounted on the upper frame about an axis of a rotation of the upper frame, i.e., in association with the rotation of the upper frame. The gear has a cam portion. One end of a lever comes into contact with part of the cam portion of the gear, while the opposite end of the lever comes into contact with a coil spring. Further, a distance from the pivotal axis of the gear to the contact position of the lever with the cam portion decreases in accordance with a proceeding of the closing operation. Accordingly, as the lever (cam follower) follows the cam portion in accordance with the closing operation of the upper frame, a compression force to compress the coil spring increases. Thereby, a brake force applied to the upper frame on the way of closing also increases.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: January 12, 1999
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Makoto Eki, Masayuki Mizuno, Susumu Taniguchi, Hideaki Kimata, Keiji Ban, Hiroyuki Arima, Katsuhide Yamaguchi
  • Patent number: 5852677
    Abstract: An image data processing apparatus is provided which is capable of properly reproducing an input image by performing a simple and short-time process in accordance with the density and type of the input image. If the minimum value of inputted image data is not higher than a first threshold, the minimum value of the inputted image data is adopted as a minimum input value to be inputted to an image outputting apparatus. If the minimum value of the inputted image data is higher than the first threshold, a lower limit input image data value is adopted as the minimum input value. Further, if the maximum value of the inputted image data is not lower than a second threshold which is higher than the first threshold, the maximum value of the inputted image data is adopted as a maximum input value to be inputted to the image outputting apparatus. If the maximum value of the inputted image data is lower than the second threshold, an upper limit input image data value is adopted as the maximum input value.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: December 22, 1998
    Assignee: Mita Industrial Co., Ltd
    Inventors: Koji Nakamura, Masayuki Mizuno
  • Patent number: 5801570
    Abstract: A plurality of MOS transistors connected to each other at a substrate electrode thereof to have a substrate potential are deviation-compensated by a combination of a power source having a power source potential independent from the substrate potential, a power supply line connected to a source electrode of each of the MOS transistors, a sample circuit composed of a sampled one of the MOS transistors, detection circuitry for detecting an action of the sample circuit to provide a detection signal representing a difference between the detected action of the sample circuit and a reference action therefor, and a voltage generator connected between the power source and the power supply line, the voltage generator generating a voltage depending on the detection signal.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: September 1, 1998
    Assignee: NEC Corporation
    Inventors: Masayuki Mizuno, Masakazu Yamashina
  • Patent number: 5790261
    Abstract: A color correcting device and a color correcting method in an image forming apparatus such as a color copying machine that rely on, a correction factor in a masking equation which is previously found for each predetermined hue range. It is judged which of a plurality of predetermined hue ranges corresponds to a hue corresponding to input data composed of color data in a plurality of colors. The input data is subjected to color correction using a masking equation using a correction factor corresponding to the judged hue range.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: August 4, 1998
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Shinji Hayashi, Masayuki Mizuno, Haruo Yamamoto
  • Patent number: 5789942
    Abstract: A level converting circuit includes a first power supply line of a high potential, a second power supply line of a low potential, a third power supply line of a potential lower than that of the first power supply line by some degree, and a first internal power supply line. The level converting circuit also includes an inverter circuit configured to output an output potential equal to that of the second power supply line when an input signal is equal to a potential of the third power supply line, and another output potential equal to that of the first power supply line when the input signal is equal to a potential of the second power supply line.
    Type: Grant
    Filed: September 9, 1996
    Date of Patent: August 4, 1998
    Assignee: NEC Corporation
    Inventor: Masayuki Mizuno
  • Patent number: 5754312
    Abstract: Disclosed is an apparatus for detecting pixels in a dotted image area (dotted area pixels). Image data corresponding to each of the pixels is coded into one of a predetermined number of discrete values. The distance between change points at which the value of the pixel after the coding is changed from a first value to a second value is detected. Further, it is examined whether or not periodicity is recognized in the distance between the change points in the vicinity of a target pixel. If periodicity is recognized in the distance between the change points, it is judged that the target pixel may constitute a dotted image area.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: May 19, 1998
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Masaya Fujimoto, Haruo Yamamoto, Masayuki Mizuno, Hidechika Kumamoto, Shinji Hayashi
  • Patent number: 5742195
    Abstract: A plurality of MOS transistors connected to each other at a substrate electrode thereof to have a substrate potential are deviation-compensated by a combination of a power source having a power source potential independent from the substrate potential, a power supply line connected to a source electrode of each of the MOS transistors, a sample circuit composed of a sampled one of the MOS transistors, detection circuitry for detecting an action of the sample circuit to provide a detection signal representing a difference between the detected action of the sample circuit and a reference action therefor, and a voltage generator connected between the power source and the power supply line, the voltage generator generating a voltage depending on the detection signal.
    Type: Grant
    Filed: February 2, 1996
    Date of Patent: April 21, 1998
    Assignee: NEC Corporation
    Inventors: Masayuki Mizuno, Masakazu Yamashina
  • Patent number: 5729627
    Abstract: An apparatus for and a method of judging a dotted image area using a small-capacity memory. Image data corresponding to one line out of image data representing an original image are stored in a line memory. On the line corresponding to the image data stored in the line memory, a target pixel is successively set along the main scanning direction. Image data corresponding to the target pixel is compared with image data corresponding to pixels around the target pixel. It is judged whether or not the target pixel is a peculiar point pixel on the basis of the result of the comparison. Further, the distance between peculiar point pixels is operated. The operated distance between the peculiar point pixels is referred to a predetermined judgment basis, to judge whether or not a judging area including the finite number of pixels is a dotted image area.
    Type: Grant
    Filed: November 2, 1995
    Date of Patent: March 17, 1998
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Masayuki Mizuno, Masaya Fujimoto, Haruo Yamamoto, Hidechika Kumamoto
  • Patent number: 5726562
    Abstract: A semiconductor device includes a first power supply line of a high potential, a second power supply line of a low potential, a third power supply line which is alternatively set to a potential equal to that of the first power supply line or to a potential lower than that of the first power supply line by some degree, and a fourth power supply line which is alternatively set to a potential equal to that of the second power supply line or to a potential higher than that of the second power supply line by some degree. A substrate bias terminal of each of pMOS transistors included in a static memory cell is connected to the first power supply line, and a source of each pMOS transistor is connected to the third power supply line. A substrate bias terminal of each of nMOS transistors included in a static memory cell is connected to the second power supply line, and a source of each pMOS transistor is connected to the fourth power supply line.
    Type: Grant
    Filed: September 9, 1996
    Date of Patent: March 10, 1998
    Assignee: NEC Corporation
    Inventor: Masayuki Mizuno
  • Patent number: 5708396
    Abstract: Disclosed is a voltage-controlled oscillator which has delay units 11A which have variable resistance circuits 111 and are connected in the form of a ring, and control signal lines 5, 6 for transmitting a control signal CG which can vary control gain. The variable resistance circuits 111 can vary the variation of resistance in response to the control signal CG.
    Type: Grant
    Filed: August 14, 1995
    Date of Patent: January 13, 1998
    Assignee: NEC Corporation
    Inventor: Masayuki Mizuno
  • Patent number: 5686853
    Abstract: The present invention provides a driver circuitry having a single input terminal for receiving an input signal of binary digits consisting of high and low levels, and at least first and second output terminals, wherein the input signal is varied almost linearly in a first time period so as to be shifted between high and low levels, the driver circuitry comprises first and second control circuits. The first control circuit is coupled to the input terminal for receiving the input signal. The first control circuit is also coupled to the first output terminal for outputting a first output signal of binary digits via the first output terminal. The first control circuit is biased between a high voltage line which supplies a high level of voltage and a low voltage line which supplies a low level of voltage.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: November 11, 1997
    Assignee: NEC Corporation
    Inventors: Tomofumi Iima, Masakazu Yamashina, Masayuki Mizuno
  • Patent number: 5670903
    Abstract: A clock signal distribution circuit provides a synchronized clock signal to a plurality of chips implementing an integrated circuit. The clock signal distribution circuit has a first and a second phase lock loop, a series of voltage controlled delay circuits and a pair of transmission lines formed between the chips. The input clock signal is transmitted from the first chip to the second chip through a transmission line, the end of which is a node supplying the output clock signal to the internal circuit of the second chip. The clock signal is then returned from the output node through the second transmission line. The first phase lock loop controls the series of voltage controlled delay circuits such that the signal at a midpoint reference node has a phase equal to the phase of the output clock signal. The second phase lock loop controls the first voltage controlled delay circuit such that the signal at the first output node has a phase synchronized with the phase of the input clock signal.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: September 23, 1997
    Assignee: NEC Corporation
    Inventor: Masayuki Mizuno
  • Patent number: 5661572
    Abstract: In one of aspects of the invention, an automatic sheet conveying mechanism comprises upper and lower casings mutually coupling sheet conveying paths in a releasable state, and a sheet guide plate for partitioning the sheet conveying paths together with the lower casing, guiding the lower surface of the sheet being conveyed, and defining the projecting extent of the functional parts supported by the lower casing into the sheet conveying path, in which the sheet guide plate is formed integrally with the lower casing.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: August 26, 1997
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Shinji Kameyama, Takeo Yoshihiro, Yoshiki Aoyama, Shuichi Akedo, Masayuki Mizuno
  • Patent number: 5629651
    Abstract: A phase lock loop has a lock detection circuit, a phase comparator, a charge pump circuit, a low-pass filter, a variable delay circuit and a frequency divider. The lock detection circuit generates a lock detection signal when a phase difference between an input reference clock and an output of the variable delay circuit is smaller than a predetermined value in a first stage of the synchronization operation. The input and output of the variable delay circuit are connected in a loop responding to the lock detection signal to form a voltage controlled oscillator (VCO) and shift the phase lock loop into a second stage of the synchronization operation. An initial control signal for controlling the VCO in the second stage is obtained as a value of the variable delay circuit in the first stage before generation of the lock detection signal, thereby obtaining a higher-speed synchronization operation and low jitters in the output clock.
    Type: Grant
    Filed: August 3, 1995
    Date of Patent: May 13, 1997
    Assignee: NEC Corporation
    Inventor: Masayuki Mizuno