Abstract: A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array of fins disposed thereon. Spacers are then formed on sidewalls of fins of the array. Pillars are formed between and adjacent the spacers. A gate having dummy gate material is formed over the structure, the gate extending laterally across the spacers and fins of the array. The dummy gate material and spacers are removed from the gate to form work-function (WF) metal trenches defined by the pillars and fins within the gate. The WF metal trenches have a first trench width. A thickness of the pillars is adjusted to provide a second trench width, different from the first trench width, for the WF metal trenches. A WF metal structure is disposed within the WF metal trenches.

Abstract: Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor. In another embodiment, the first transistor includes a fin structure extending from the substrate, and an upper portion of the fin structure includes the first channel region and a lower portion of the fin structure includes the isolation region.

Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pull-up (PU1) transistor and a second pull-up (PU2) transistor. The at least one CBP facilitates biasing of at least one the PU1 and PU2 transistors during at least one of a read, write or standby operation of the structures.

Abstract: A method of forming a semiconductor structure, comprising forming a dual damascene structure having a capacitor trench and an interconnect trench, forming a first electrode a dielectric of the capacitor, and, depositing a metal within said capacitor trench and said interconnection trench wherein the metal forms a second electrode of the capacitor and also forms an interconnection between layers of an interconnecting structure of a semiconductor device.

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

Abstract: A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array of fins disposed thereon. Spacers are then formed on sidewalls of fins of the array. Pillars are formed between and adjacent the spacers. A gate having dummy gate material is formed over the structure, the gate extending laterally across the spacers and fins of the array. The dummy gate material and spacers are removed from the gate to form work-function (WF) metal trenches defined by the pillars and fins within the gate. The WF metal trenches have a first trench width. A thickness of the pillars is adjusted to provide a second trench width, different from the first trench width, for the WF metal trenches. A WF metal structure is disposed within the WF metal trenches.

Abstract: A method of forming a semiconductor structure, comprising forming a dual damascene structure having a capacitor trench and an interconnect trench, forming a first electrode a dielectric of the capacitor, and, depositing a metal within said capacitor trench and said interconnection trench wherein the metal forms a second electrode of the capacitor and also forms an interconnection between layers of an interconnecting structure of a semiconductor device.

Abstract: A method includes, for example, a starting semiconductor structure comprising a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a first protective layer over some of the plurality of material lines, the protected material lines and the unprotected material lines having a same corresponding first critical dimension, oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased second critical dimension greater than the first critical dimension, removing the first protective layer, forming a second protective layer over some of the plurality of protected material lines having the first critical dimension and some of the oxidized material lines having the second critical dimension, and oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased third critical dimension greater than the first critical dimension.

Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pull-down (PD1) transistor and a second pull-down (PD2) transistor. The at least one CBP facilitates biasing at least one of the PD1 and PD2 transistors during at least one of a read, write or standby operation of the structures.

Abstract: A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.

Abstract: A method includes, for example, a starting semiconductor structure comprising a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a first protective layer over some of the plurality of material lines, the protected material lines and the unprotected material lines having a same corresponding first critical dimension, oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased second critical dimension greater than the first critical dimension, removing the first protective layer, forming a second protective layer over some of the plurality of protected material lines having the first critical dimension and some of the oxidized material lines having the second critical dimension, and oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased third critical dimension greater than the first critical dimension.

Abstract: Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess. An intermediate semiconductor device is also disclosed.

Abstract: A method includes, for example, providing a starting semiconductor structure having a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a protective layer over a portion of at least one material line, the at least one protected material line and at least one unprotected material line having a same critical dimension, oxidizing the at least one unprotected material line to increase the critical dimension compared to the first critical dimension of the at least one protected material line, and etching at least a portion of the oxidized unprotected material line so that the etched critical dimension of the at least one etched material line is different from the first critical dimension of the at least one protected material line.

Abstract: A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced.

Abstract: Disclosed are methods for stress memorization techniques. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.

Abstract: Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a substrate, the first semiconductor region having a first conductivity type; and a second semiconductor region disposed at least partially within the first semiconductor region, the second semiconductor region having a second conductivity type, wherein the first semiconductor region separates the second semiconductor region from the substrate. In one embodiment, the substrate and the first semiconductor region have a sigma-shaped boundary. In another embodiment, the substrate and the first semiconductor region have U-shaped boundary.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming sidewall spacer structures laterally adjacent to a dummy gate structure that overlies a semiconductor substrate. Additional sidewall spacer structures are formed laterally adjacent to the sidewall spacer structures and under lower portions of the sidewall spacer structures. The dummy gate structure is replaced with a replacement gate structure.

Abstract: A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.

Abstract: Structures for contacting a fin-type field-effect transistor (FinFET) and associated methods. First and second gate structures are formed. The second gate structure is separated from the first gate structure by a space that crosses over a top surface of a fin. At least one layer is formed in the space, and a hardmask layer is formed on the at least one layer. An opening is formed in the hardmask layer at a location that is above the top surface of the fin and that is between the first gate structure and the second gate structure. The at least one layer is etched at the location of the opening to form a contact hole extending through the at least one layer to the top surface of the fin. A contact, which is formed in the contact hole, is coupled with the top surface of the fin.

Abstract: Methods of fabricating field effect transistors having a source region and a drain region separated by a channel region are provided which include: using a single mask step in forming a first portion(s) and a second portion(s) of at least one of the source region or the drain region, the first portion(s) including a first material selected and configured to facilitate the first portion(s) stressing the channel region, and the second portion(s) including a second material selected and configured to facilitate the second portion(s) having a lower electrical resistance than the first portion(s). One embodiment includes: providing the first material with a crystal lattice structure; and forming the second material by disposing another material interstitially with respect to the crystal lattice structure. Another embodiment includes forming the first portion and the second portion within at least one of a source cavity or a drain cavity of the semiconductor substrate.