Patents by Inventor Min-Hwa Chi

Min-Hwa Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SRAM bitcell structures facilitating biasing of pass gate transistors
    Patent number: 9734897
    Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pass gate (PG1) transistor and a second pass gate (PG2) transistor. The at least one CBP facilitates biasing of at least one the PG1 and PG2 transistors during at least one of a read, write or standby operation of the structures.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: August 15, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Manfred Eller, Min-hwa Chi
  • MODIFIED TUNNELING FIELD EFFECT TRANSISTORS AND FABRICATION METHODS
    Publication number: 20170230004
    Abstract: Tunneling field effect transistors and fabrication methods thereof are provided, which include: an integrated circuit device which includes a circuit input configured to receive an input voltage and a circuit output configured to deliver an output current. The integrated circuit also includes a circuit element having at least one tunneling field effect transistor (TFET). The circuit element connects the circuit input to the circuit output and is characterized by a V-shaped current-voltage diagram. The V-shaped current-voltage diagram describes the relationship between the input voltage of the circuit input and the output current of the circuit output.
    Type: Application
    Filed: April 25, 2017
    Publication date: August 10, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yanxiang LIU, Min-hwa CHI
  • METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES
    Publication number: 20170221823
    Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Inventors: Suraj Kumar Patil, Min-Hwa Chi
  • TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOF
    Publication number: 20170213890
    Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.
    Type: Application
    Filed: April 7, 2017
    Publication date: July 27, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xusheng WU, Jin Ping LIU, Min-hwa CHI
  • Devices and methods for dynamically tunable biasing to backplates and wells
    Patent number: 9716138
    Abstract: Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess. An intermediate semiconductor device is also disclosed.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: July 25, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Min-hwa Chi
  • SELF-ALIGNED SOURCE/DRAIN CONTACT IN REPLACEMENT METAL GATE PROCESS
    Publication number: 20170207118
    Abstract: A starting semiconductor structure for a RMG process includes a semiconductor substrate, transistors in process having dummy gates and electrically isolated by isolation regions. The dummy gates are replaced with metal gates and gate caps, the structure being planarized after replacing the gate. A cap layer is formed over the planarized structure, and trenches are formed through the cap to expose source and drain regions of the transistors, which allows for self-aligned source and drain contacts. Semiconductor structures including the source and drain trenches for self-aligned source/drain contacts are also presented.
    Type: Application
    Filed: January 14, 2016
    Publication date: July 20, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Wen Pin PENG, Min-hwa CHI, Yue HU
  • STRESS MEMORIZATION AND DEFECT SUPPRESSION TECHNIQUES FOR NMOS TRANSISTOR DEVICES
    Publication number: 20170207090
    Abstract: In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.
    Type: Application
    Filed: January 19, 2016
    Publication date: July 20, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Wen-Pin PENG, Min-hwa CHI
  • MULTIPLE THRESHOLD VOLTAGES USING FIN PITCH AND PROFILE
    Publication number: 20170207216
    Abstract: A multi-Vt FinFET includes a semiconductor substrate, multiple first fins coupled to the semiconductor substrate having a first fin pitch, and multiple second fins coupled to the semiconductor substrate having a second fin pitch larger than the first fin pitch. The semiconductor structure further includes transistor(s) on the multiple first fins, and transistor(s) on the multiple second fins, a threshold voltage of the transistor(s) on the multiple second fins being higher than that of the transistor(s) on the multiple first fins.
    Type: Application
    Filed: January 20, 2016
    Publication date: July 20, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Wen Pin PENG, Min-hwa CHI
  • Stress memorization and defect suppression techniques for NMOS transistor devices
    Patent number: 9711619
    Abstract: In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: July 18, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wen-Pin Peng, Min-hwa Chi
  • FABRICATION OF TRANSISTOR-BASED SEMICONDUCTOR DEVICE USING CLOSED-LOOP FINS
    Publication number: 20170200786
    Abstract: Shaped mandrels are used to form closed-loop spacer(s) around the shaped mandrels, after which the shaped mandrels are removed, leaving a closed-loop fin. A transistor includes U-shaped portion(s) of a closed-loop fin, and a gate across channel region(s) of the U-shaped portion(s) of a closed-loop fin. A semiconductor structure includes portion(s) of closed-loop fin(s), and transistors formed from the portion(s) of closed-loop fin(s).
    Type: Application
    Filed: January 12, 2016
    Publication date: July 13, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Hui ZANG, Min-hwa CHI
  • Methods of forming CMOS based integrated circuit products using disposable spacers
    Patent number: 9704759
    Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wen Pin Peng, Min-hwa Chi, Garo Jacques Derderian
  • Conformal nitridation of one or more fin-type transistor layers
    Patent number: 9698269
    Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: July 4, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wei Hua Tong, Tien-Ying Luo, Yan Ping Shen, Feng Zhou, Jun Lian, Haoran Shi, Min-hwa Chi, Jin Ping Liu, Haiting Wang, Seung Kim
  • Integrated circuits with replacement metal gates and methods for fabricating the same
    Patent number: 9698241
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one embodiment, a method for fabricating integrated circuits includes forming a gate dielectric overlying a substrate, and forming a base work function layer that includes tungsten overlying the gate dielectric. The base work function layer overlies the gate dielectric in a first and second region, where the first region is one of a pFET region or an nFET region and the second region is the other of the pFET region or the nFET region. A mask is formed over the first region, and then the second region is exposed. A work function value of the base work function layer in the second region is altered to produce a modified work function layer. The mask is removed from the over the first region, and a gate electrode is formed overlying the base and modified work function layers.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 4, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Suraj K. Patil, Min-Hwa Chi, Mitsuhiro Togo
  • Programmable devices with current-facilitated migration and fabrication methods
    Patent number: 9691497
    Abstract: Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 27, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Suraj K. Patil, Min-hwa Chi, Ajey P. Jacob
  • Modified tunneling field effect transistors and fabrication methods
    Patent number: 9673757
    Abstract: Tunneling field effect transistors and fabrication methods thereof are provided, which include: obtaining a gate structure disposed over a substrate structure; and providing a source region and a drain region within the substrate structure separated by a channel region, the channel region underlying, at least partially, the gate structure, and the providing including: modifying the source region to attain a narrowed source region bandgap; and modifying the drain region to attain a narrowed drain region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers from the source region or the drain region to the channel region. Devices including digital modulation circuits with one or more tunneling field effect transistor(s) are also provided.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: June 6, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanxiang Liu, Min-hwa Chi
  • Method, apparatus, and system for e-fuse in advanced CMOS technologies
    Patent number: 9659862
    Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: May 23, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj Kumar Patil, Min-Hwa Chi
  • SEMICONDUCTOR FUSES WITH NANOWIRE FUSE LINKS AND FABRICATION METHODS THEREOF
    Publication number: 20170141031
    Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.
    Type: Application
    Filed: February 1, 2017
    Publication date: May 18, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Chun Yu WONG, Jagar SINGH, Ashish BARASKAR, Min-hwa CHI
  • METHOD, APPARATUS AND SYSTEM FOR IMPROVED PERFORMANCE USING TALL FINS IN FINFET DEVICES
    Publication number: 20170141214
    Abstract: At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A first fin of a transistor is formed. The first fin comprising a first portion comprising silicon, a second portion comprising silicon germanium and a third portion comprising silicon. A gate structure above the third portion is formed. An etching process is performed for removing the silicon germanium of the second portion that is not below the gate structure. A first epitaxy region is formed above the first portion. A second epitaxy region is formed vertically aligned with the first epitaxy region and above the second region.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 18, 2017
    Applicant: GLOBAFOUNDRIES INC.
    Inventors: Hui Zang, Min-Hwa Chi, Jinping Liu
  • Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices
    Patent number: 9653583
    Abstract: One illustrative method disclosed herein includes, among other things, forming a first gate structure above a fin, forming epi semiconductor material on the fin, performing at least one first etching process through a patterned sacrificial layer of material to remove at least a gate cap layer and sacrificial gate materials of the first gate structure so as to define a first isolation cavity that exposes the fin while leaving the second gate structure intact, performing at least one second etching process through the first isolation cavity to remove at least a portion of a vertical height of the fin and thereby form a first isolation trench, removing the patterned sacrificial layer of material, and forming a layer of insulating material above the epi semiconductor material and in the first isolation trench and in the first isolation cavity.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: May 16, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wei Zhao, Haiting Wang, Hongliang Shen, Zhenyu Hu, Min-Hwa Chi
  • METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES
    Publication number: 20170133319
    Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.
    Type: Application
    Filed: November 9, 2015
    Publication date: May 11, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Suraj Kumar Patil, Min-Hwa Chi