Patents by Inventor Min-Hwa Chi

Min-Hwa Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology
    Patent number: 9418899
    Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: August 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yan Ping Shen, Min-hwa Chi, Xusheng Wu, Weihua Tong, Haiting Wang
  • METHODS OF FABRICATING NANOWIRE STRUCTURES
    Publication number: 20160225849
    Abstract: Methods are presented for fabricating nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate and forming a fin above the substrate so that the fin has a first sidewall including one or more elongate first sidewall protrusions and a second sidewall including one or more elongate second sidewall protrusions, with the one or more elongate second sidewall protrusions being substantially aligned with the one or more elongate first sidewall protrusions; and, anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires. The etchant may be chosen to selectively etch along a pre-defined crystallographic plane, such as the (111) crystallographic plane, to form the nanowire structures.
    Type: Application
    Filed: February 4, 2015
    Publication date: August 4, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Chun Yu WONG, Min-hwa CHI, Ashish BARASKAR, Jagar SINGH
  • METHOD OF MULTI-WF FOR MULTI-VT AND THIN SIDEWALL DEPOSITION BY IMPLANTATION FOR GATE-LAST PLANAR CMOS AND FINFET TECHNOLOGY
    Publication number: 20160225675
    Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.
    Type: Application
    Filed: February 2, 2015
    Publication date: August 4, 2016
    Inventors: Yan Ping SHEN, Min-hwa CHI, Xusheng WU, Weihua TONG, Haiting WANG
  • FABRICATING TRANSISTORS HAVING RESURFACED SOURCE/DRAIN REGIONS WITH STRESSED PORTIONS
    Publication number: 20160225852
    Abstract: Methods are providing for fabricating transistors having at least one source region or drain region with a stressed portion. The methods include: forming, within a cavity of a substrate structure, the at least one source region or drain region with the internal stress; and resurfacing the at least one source region or drain region to reduce surface defects of the at least one source region or drain region without relaxing the stressed portion thereof. For instance, the resurfacing can include melting an upper portion of the at least one source region or drain region. In addition, the resurfacing can include re-crystallizing an upper portion of the at least one source region or drain region, and/or providing the at least one source region or drain region with at least one {111} surface.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 4, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Shishir RAY, Bharat KRISHNAN, Min-hwa CHI
  • BIPOLAR TRANSISTOR, BAND-GAP REFERENCE CIRCUIT AND VIRTUAL GROUND REFERENCE CIRCUIT
    Publication number: 20160218194
    Abstract: The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 28, 2016
    Inventors: MIN-HWA CHI, LIHYING CHING, DEYUAN XIAO
  • FINFET WITH MULTILAYER FINS FOR MULTI-VALUE LOGIC (MVL) APPLICATIONS AND METHOD OF FORMING
    Publication number: 20160211375
    Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventors: Min-hwa CHI, Ajey JACOB, Abhijeet PAUL
  • MOL contact metallization scheme for improved yield and device reliability
    Patent number: 9396995
    Abstract: A method of forming a metalized contact in MOL is provided. Embodiments include forming a TT through an ILD down to a S/D region; forming a SiOC, SiCN, or SiON layer on side surfaces of the TT; performing a GCIB vertical etching at a 0° angle; implanting Si into the TT by an angled PAI; removing a portion of the TT by Ar sputtering and a remote plasma assisted dry etch process; forming NiSi on the S/D region at the bottom of the TT; and filling the TT with contact metal over the NiSi.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: July 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj K. Patil, Min-hwa Chi, Garo Derderian, Wen-Pin Peng
  • Silicon-on-insulator finFET with bulk source and drain
    Patent number: 9385126
    Abstract: Embodiments of the invention provide a semiconductor structure including a finFET having an epitaxial semiconductor region in direct physical contact with a plurality of fins, wherein the epitaxial semiconductor region traverses an insulator layer and is in direct physical contact with the semiconductor substrate. The gate of the finFET is disposed over an insulator layer, such as a buried oxide layer. Methods of forming the semiconductor structure are also included.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: July 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanxiang Liu, Min-hwa Chi
  • Methods of forming reduced thickness spacers in CMOS based integrated circuit products
    Patent number: 9385124
    Abstract: One method disclosed herein includes, among other things, forming a first spacer proximate gate structures of first and second transistors that are opposite type transistors, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, performing a timed, wet etching process on both of the transistors so as to completely remove the layer of second spacer material from the second transistor while leaving a reduced thickness second spacer positioned adjacent the first spacer of the first transistor, wherein the reduced thickness second spacer has a thickness that is less than an initial thickness of the initial second spacer, and forming a third spacer on and in contact with the first spacer of the second transistor.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 5, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wen Pin Peng, Min-hwa Chi, Garo Jacques Derderian
  • FABRICATION METHODS FOR MULTI-LAYER SEMICONDUCTOR STRUCTURES
    Publication number: 20160190014
    Abstract: Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a substrate, the first layer including a first metal and the second layer including a second metal, where the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first layer, the second layer, and the substrate to react at least a portion of the first metal of the first layer to form a first reacted layer and at least a portion of the second metal of the second layer to form a second reacted layer, where at least one of the first reacted layer or the second reacted layer includes at least one of a first metal silicide of the first metal or a second metal silicide of the second metal.
    Type: Application
    Filed: June 4, 2015
    Publication date: June 30, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Suraj K. PATIL, Min-hwa CHI
  • CONFORMAL NITRIDATION OF ONE OR MORE FIN-TYPE TRANSISTOR LAYERS
    Publication number: 20160190324
    Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.
    Type: Application
    Filed: March 3, 2016
    Publication date: June 30, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Wei Hua TONG, Tien-Ying LUO, Yan Ping SHEN, Feng ZHOU, Jun LIAN, Haoran SHI, Min-hwa CHI, Jin Ping LIU, Haiting WANG, Seung KIM
  • Selectively forming a protective conductive cap on a metal gate electrode
    Patent number: 9379209
    Abstract: A replacement gate structure that includes a conductive metal gate electrode is formed in a gate cavity, wherein the gate cavity is formed in a dielectric material formed above an active region of a semiconductor device. An upper surface of the conductive metal gate electrode and an upper surface of the dielectric material are planarized during a common planarization process, and a protective conductive cap is selectively formed on and in direct physical contact with the planarized upper surface of the conductive metal gate electrode. A contact structure is formed in a dielectric insulating layer formed above the replacement gate structure, the contact structure directly contacting the protective conductive cap.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: June 28, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Jiajun Mao, Xusheng Wu, Min-hwa Chi
  • Fet structure for minimum size length/width devices for performance boost and mismatch reduction
    Patent number: 9379186
    Abstract: Methods for preparing CMOS transistors having longer effective gate lengths and the resulting devices are disclosed. Embodiments include forming a dummy gate bound by spacers on opposing sides thereof, on a substrate; removing the dummy gate to form a trench between the spacers; modifying a gate channel portion of the substrate between the spacers to form inner or outer sidewalls; depositing a conformal high-k dielectric layer on the modified gate channel portion; and forming a metal gate in the trench.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: June 28, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qin Wang, Min-hwa Chi, Meixiong Zhao, Zhaoxu Shen, Haiting Wang, Lucas M. Salazar, Lan Yang
  • INTEGRATED CIRCUITS INCLUDING REPLACEMENT GATE STRUCTURES AND METHODS FOR FABRICATING THE SAME
    Publication number: 20160163824
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming sidewall spacer structures laterally adjacent to a dummy gate structure that overlies a semiconductor substrate. Additional sidewall spacer structures are formed laterally adjacent to the sidewall spacer structures and under lower portions of the sidewall spacer structures. The dummy gate structure is replaced with a replacement gate structure.
    Type: Application
    Filed: December 4, 2014
    Publication date: June 9, 2016
    Inventors: Dong-Woon Shin, Min-Hwa Chi, Xusheng Wu
  • FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming
    Patent number: 9362277
    Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNRIES INC.
    Inventors: Min-hwa Chi, Ajey Jacob, Abhijeet Paul
  • SELECTIVELY FORMING A PROTECTIVE CONDUCTIVE CAP ON A METAL GATE ELECTRODE
    Publication number: 20160133721
    Abstract: A replacement gate structure that includes a conductive metal gate electrode is formed in a gate cavity, wherein the gate cavity is formed in a dielectric material formed above an active region of a semiconductor device. An upper surface of the conductive metal gate electrode and an upper surface of the dielectric material are planarized during a common planarization process, and a protective conductive cap is selectively formed on and in direct physical contact with the planarized upper surface of the conductive metal gate electrode. A contact structure is formed in a dielectric insulating layer formed above the replacement gate structure, the contact structure directly contacting the protective conductive cap.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 12, 2016
    Inventors: Xiuyu Cai, Jiajun Mao, Xusheng Wu, Min-hwa Chi
  • Bipolar transistor, band-gap reference circuit and virtual ground reference circuit
    Patent number: 9337324
    Abstract: The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: May 10, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Min-Hwa Chi, Lihying Ching, Deyuan Xiao
  • FinFET with active region shaped structures and channel separation
    Patent number: 9337340
    Abstract: A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: May 10, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min-Hwa Chi, Hoong Shing Wong
  • EMBEDDED DRAM IN REPLACEMENT METAL GATE TECHNOLOGY
    Publication number: 20160126245
    Abstract: Methods for forming an eDRAM with replacement metal gate technology and the resulting device are disclosed. Embodiments include forming first and second dummy electrodes on a substrate, each dummy electrode having spacers at opposite sides and being surrounded by an ILD; removing the first and second dummy electrodes, forming first and second cavities, respectively; forming a hardmask over the substrate, exposing the first cavity; forming a deep trench in the substrate through the first cavity; removing the hardmask; and forming a capacitor in the first cavity and deep trench and concurrently forming an access transistor in the second cavity.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 5, 2016
    Inventors: Yanxiang LIU, Min-hwa CHI
  • TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOF
    Publication number: 20160126316
    Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 5, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xusheng WU, Jin Ping LIU, Min-hwa CHI