Abstract: A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.

Abstract: A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.

Abstract: An electronic device is provided. The electronic device includes a memory and at least one processor configured to execute a first application among at least one application stored in the memory, determine whether to permit to provide meta information including information for accessing first data related to a first function of the first application stored in the memory based on first user information with which the first application is executed, and perform control as to whether to provide a virtual file system with the meta information about the first data.

Abstract: A semiconductor device is provided which includes a first fin-type pattern including a first side surface and a second side surface opposite to each other, a first trench of a first depth adjacent to the first side surface, a second trench of a second depth adjacent to the second side surface. The second depth differs from the first depth, and a first field insulating film partially fills the first trench and a second field insulating film partially fills the second trench. The first fin-type pattern has a lower portion, and an upper portion having a narrower width than the lower portion, and has a first stepped portion on a boundary between the upper portion and the lower portion. The first field insulating film includes a first lower field insulating film in contact with the lower portion, and a first upper field insulating film in contact with the upper portion.

Abstract: A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.

Abstract: An integrated circuit device includes a fin-type active area extending on a substrate in a first direction, a first gate line and a second gate line extending on the fin-type active area in parallel to each other in a second direction, which is different from the first direction, a first insulating capping layer covering an upper surface of the first gate line and extending in parallel to the first gate line, a second insulating capping layer covering an upper surface of the second gate line and extending in parallel to the second gate line, wherein a height of the first gate line and a height of the second gate line are different from each other.

Abstract: A tin compound, tin precursor compound for atomic layer deposition (ALD), a method of forming a tin-containing material film, and a method of synthesizing a tin compound, the tin compound being represented by Chemical Formula (I): wherein R1, R2, Q1, Q2, Q3, and Q4 are each independently a Cl to C4 linear or branched alkyl group.

Abstract: A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.

Abstract: A semiconductor device includes a substrate including first to third regions, wherein the third region is positioned in a first direction between the first and second regions, a fin protruding on the substrate and extending in the first direction, first and second gate structures respectively formed on the fin in the first and second regions, first and second spacers formed with spacing apart from each other on the fin in the third region. The first and second spacers are sloped in a direction away from each other, and the first and second spacers and an upper surface of the fin define a plurality of acute angles, the first and second spacers defining a recess, the fin and the first and second spacers defining sidewalls of the recess, and a device isolating film substantially filling the recess.

Abstract: A semiconductor device is provided that includes a deep trench defining an active region, and a fin-type pattern protruding within the active region. The fin-type pattern having a lower portion, an upper portion of a narrower width than the lower portion, and a first stepped portion formed at a boundary between the upper portion and the lower portion. The device also includes a first field insulating film surrounding the lower portion and a second field insulating film formed on the first field insulating film and partially surrounding the upper portion.

Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

Abstract: A light-emitting element disclosed in an embodiment comprises: a body having a cavity; first and second lead frames arranged in the cavity; a third lead frame arranged between the first and second lead frames in the cavity; a fourth lead frame arranged between the first and second lead frames and distanced from the third frame in the cavity; a first light-emitting chip arranged on the first lead frame; and a second light-emitting chip arranged on the second lead frame, wherein the body comprises: first and second sides arranged on opposing sides from each other; and third and fourth sides arranged on opposing sides from each other, the first lead frame comprises first and second lead parts protruding toward the first and second sides, the second lead frame comprises third and forth lead parts protruding toward the first and second sides, the third frame comprises a fifth lead part protruding toward the first side, and the fourth lead frame comprises a sixth lead part protruding toward the second side.

Abstract: There is provided an electrode assembly having increased degrees of structural freedom in the thickness direction thereof. The electrode assembly includes negative and positive electrodes alternately stacked with separators interposed therebetween, wherein the electrode assembly is formed by stacking N electrode stacks where N is a natural number equal to or greater than 2, each of the electrode stacks comprises electrodes having the same area and stacked with separators interposed therebetween, and neighboring electrode stacks of the electrode stacks have different electrode areas, wherein a first electrode stack of the electrode stacks is formed by stacking unit cells respectively including an odd number of electrodes, and the other electrode stacks stacked on the first electrode are formed by stacking unit cells respectively including an even number of electrodes.

Abstract: A semiconductor device is provided that includes a deep trench defining an active region, and a fin-type pattern protruding within the active region. The fin-type pattern having a lower portion, an upper portion of a narrower width than the lower portion, and a first stepped portion formed at a boundary between the upper portion and the lower portion. The device also includes a first field insulating film surrounding the lower portion and a second field insulating film formed on the first field insulating film and partially surrounding the upper portion.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

Abstract: A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.

Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively, forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region, forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid, and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.

Abstract: An operation method of a semiconductor memory device including a memory cell array and an internal processor configured to perform an internal processing operation includes receiving at the memory device a first mode indicator that indicates whether the memory device should operate in a processor mode or in a normal mode, receiving at the memory device processing information for the memory device, when the first mode indicator indicates that the memory device should operate in the processor mode, storing the processing information in a first memory cell region of the memory cell array, using the stored processing information to perform internal processing by the internal processor, and storing a result of the internal processing in the memory cell array.

Abstract: An integrated circuit device includes a fin-type active area extending on a substrate in a first direction, a first gate line and a second gate line extending on the fin-type active area in parallel to each other in a second direction, which is different from the first direction, a first insulating capping layer covering an upper surface of the first gate line and extending in parallel to the first gate line, a second insulating capping layer covering an upper surface of the second gate line and extending in parallel to the second gate line, wherein a height of the first gate line and a height of the second gate line are different from each other.

Abstract: A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.