Patents by Inventor Min Ryu

Min Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Light emitting device and light unit having the same
    Patent number: 9793249
    Abstract: A light emitting device is provided. The light emitting device may include a body, first and second lead frames coupled to the body, a first light emitting chip on the first lead frame, a second light emitting chip on the second lead frame, and a reflective frame on the body and the first and second lead frames. The reflective frame may include a first opening provided therein with the first light emitting chip and a second opening provided therein with the second light emitting chip.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: October 17, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Tae Sung Lee, Young Min Ryu, Jae Hwan Jung, Jong Beom Choi
  • Method for eliciting plant immune responses by seed priming of heat-treated Bacillus culture solution
    Patent number: 9781938
    Abstract: The present invention relates to a method of eliciting plant immune responses based on seed priming by using the heat (high temperature)-treated culture solution of Bacillus spp, and the high pressure-sterilized culture solution of Bacillus sp. strains PB69 and 1628 which have been selected in the present invention exhibits an activity of eliciting induced systemic resistance similar to BTH, and also has an effect for inducing promoted plant growth and controlling plant diseases, and thus it is expected to contribute to enhance the crop productivity.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: October 10, 2017
    Assignee: KOREA RESEARCH INSTITUTE OF BIOSCIENCE AND BIOTECHNOLOGY
    Inventors: Choong Min Ryu, Geun Cheol Song
  • INTEGRATED CIRCUIT AND COMPUTER-IMPLEMENTED METHOD OF MANUFACTURING THE SAME
    Publication number: 20170236814
    Abstract: A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.
    Type: Application
    Filed: January 31, 2017
    Publication date: August 17, 2017
    Inventors: SEONG-MIN RYU, HYO-SIG WON
  • Electrode assembly, battery cell, manufacturing method of electrode assembly, and manufacturing method of battery cell
    Patent number: 9728758
    Abstract: The present invention relates to a method of manufacturing an electrode assembly, the method including: preparing an electrode laminate including at least one negative electrode, at least one positive electrode, and at least one separation film; generating a separation film assembly by bonding remaining portions of the separation film positioned in regions not corresponding to shapes of the negative electrode and the positive electrode; and cutting the separation film assembly so as to correspond to the shapes of the negative electrode and the positive electrode, and an electrode assembly manufactured by the method.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 8, 2017
    Assignee: LG Chem, Ltd.
    Inventors: Sung-Jin Kwon, Soon-Ho Ahn, Dong-Myung Kim, Ki-Woong Kim, Young-Hoon Kim, Sung-Han Yoon, Seung-Min Ryu
  • MEMORY SYSTEM INCLUDING MEMORY DEVICE
    Publication number: 20170200507
    Abstract: A memory system includes a plurality of first signal lines to connect a plurality of memory devices to one another. The memory devices include a first memory device and at least one second memory device. The first memory device has at least one fuse cell and outputs fuse information set based on whether each of the at least one fuse cell is programmed. The at least one second memory device receives the fuse information and selectively activates the first signal lines based on the fuse information. The at least one second memory device simultaneously operates based on the fuse information received from the first memory device.
    Type: Application
    Filed: December 28, 2016
    Publication date: July 13, 2017
    Inventors: Yoon Jae JEONG, Je Min RYU
  • Electrode assembly having excellent electrode tab connectivity and battery cell and device including electrode assembly
    Patent number: 9698406
    Abstract: An electrode assembly and a method of manufacturing the same are provided. The electrode assembly includes an electrode stack including at least one anode, at least one cathode, and at least one separation film and a plurality of cathode tabs and a plurality of anode tabs for electrically connecting the electrode stack. In this case, the electrode tabs are arranged to allow the electrode tabs having the same polarity to be electrically connected to one another while a portion of the electrode tabs having the same polarity are arranged so as not to overlap one another on the same plane.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: July 4, 2017
    Assignee: LG Chem, Ltd.
    Inventors: Young-Hoon Kim, Sung-Jin Kwon, Soon-Ho Ahn, Dong-Myung Kim, Ki-Woong Kim, Seung-Min Ryu
  • TANTALUM COMPOUND AND METHODS OF FORMING THIN FILM AND FABRICATING INTEGRATED CIRCUIT DEVICE BY USING THE SAME
    Publication number: 20170178961
    Abstract: A tantalum compound, a method of forming a thin film, and a method of fabricating an integrated circuit device, the tantalum compound being represented by the following General Formula (I):
    Type: Application
    Filed: October 20, 2016
    Publication date: June 22, 2017
    Applicant: ADEKA CORPORATION
    Inventors: Seung-min RYU, Takanori KOIDE, Naoki YAMADA, Jae-soon LIM, Tsubasa SHIRATORI, Youn-joung CHO
  • Stepwise electrode assembly having variously-shaped corner and secondary battery, battery pack and device comprising the same
    Patent number: 9685679
    Abstract: There is provided an electrode assembly having steps including: a first electrode stair including at least one first electrode unit; and a second electrode stair including at least one second electrode unit having an area different from that of the first electrode unit, wherein the first electrode stair and the second electrode stair are stacked to be adjacent, separated by at least one separator as a boundary therebetween and including one or more electrode laminates having steps formed by a difference between areas of the first electrode stair and the second electrode stair, and shapes of the corners of the first electrode stair and the second electrode stair having steps are different. There is also provided a secondary battery including the electrode assembly. Secondary batteries having various designs without restriction in shapes of corners of electrode units can be provided.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 20, 2017
    Assignee: LG Chem, Ltd.
    Inventors: Seung-Min Ryu, Sung-Jin Kwon, Soon-Ho Ahn, Dong-Myung Kim, Ki-Woong Kim, Young-Hoon Kim
  • Electrode assembly having step, battery cell, battery pack and device including the same
    Patent number: 9660296
    Abstract: There is provide an electrode assembly including an electrode laminate having a plurality of electrode units rolled up to be stacked on one another in at least two rectangularly shaped separation films, the electrode assembly being characterized in that at least one of two rectangularly shaped separation films is disposed on upper and lower surfaces of the respective electrode unit, at least one separation film disposed on one surface being different from a separation film disposed on another surface, and the electrode laminate includes at least one step formed by stacking an electrode unit having a difference in area from an electrode unit adjacent thereto, having one of the rectangularly shaped separation films as a boundary therebetween.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: May 23, 2017
    Assignee: LG Chem, Ltd.
    Inventors: Young-Hoon Kim, Sung-jin Kwon, Soon-Ho Ahn, Dong-Myung Kim, Ki-Woong Kim, Seung-Min Ryu
  • SEMICONDUCTOR DEVICE
    Publication number: 20170141107
    Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.
    Type: Application
    Filed: October 25, 2016
    Publication date: May 18, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung Soo KIM, Gi Gwan PARK, Jung Hun CHOI, Koung Min RYU, Sun Jung LEE
  • CHUCK PIN, METHOD FOR MANUFACTURING A CHUCK PIN, APPARATUS FOR TREATING A SUBSTRATE
    Publication number: 20170140977
    Abstract: A chuck pin, method for manufacturing a chuck pin, and an apparatus for treating substrate. The substrate treating apparatus includes a container having a treating space in its inner side, a supporting unit supporting the substrate inside of the treating space, and a liquid supply unit providing a solution to the supported substrate of the supporting unit. The supporting unit is placed in a supporting plate where the substrate is placed and in the above supporting plate, and includes a chuck pin supporting a side part of the substrate. The chuck pin is formed on a body and on the above surface of the body, and includes a first coating film provided as a silicon carbide material.
    Type: Application
    Filed: November 16, 2016
    Publication date: May 18, 2017
    Inventors: Chong-Min Ryu, Won-Jun Lee, Seung-Ho Seo
  • SEMICONDUCTOR DEVICE HAVING CHIP ID GENERATION CIRCUIT
    Publication number: 20170125119
    Abstract: Provided is a semiconductor device including chip identification (ID) generation circuits. The semiconductor device may be a multi-chip package including a plurality of memory chips, and each of the memory chips includes a chip ID generation circuit configured to selectively modify a chip ID of a corresponding memory chip. The chip ID generation circuit determines the chip ID of the memory chip by testing the chip ID of the memory chip by using a mode register, and selectively programs the chip ID of the memory chip by using at least two fuse sets. The chip ID generation circuit may block an output of the chip ID of the memory chip when the memory chip is determined as a defective chip or is selected to stop its use.
    Type: Application
    Filed: August 9, 2016
    Publication date: May 4, 2017
    Inventors: Yang-gyoon LOH, Je-min RYU, Hyun-ki KIM, Yoon-jae JEONG
  • SEMICONDUCTOR DEVICE
    Publication number: 20170125597
    Abstract: A semiconductor device is provided which includes a first fin-type pattern including a first side surface and a second side surface opposite to each other, a first trench of a first depth adjacent to the first side surface, a second trench of a second depth adjacent to the second side surface. The second depth differs from the first depth, and a first field insulating film partially fills the first trench and a second field insulating film partially fills the second trench. The first fin-type pattern has a lower portion, and an upper portion having a narrower width than the lower portion, and has a first stepped portion on a boundary between the upper portion and the lower portion. The first field insulating film includes a first lower field insulating film in contact with the lower portion, and a first upper field insulating film in contact with the upper portion.
    Type: Application
    Filed: October 17, 2016
    Publication date: May 4, 2017
    Inventors: Sung-Soo KIM, Gi-Gwan PARK, Song-E KIM, Koung-Min RYU, Sun-Ki MIN
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20170117192
    Abstract: A semiconductor device may include a first gate electrode being formed on a substrate and having a first ratio of a width of an upper surface to a width of a lower surface, a second gate electrode being formed on the substrate and having a second ratio of the width of the upper surface to the width of the lower surface, wherein the second ratio is less than the first ratio, a first gate spacer being formed on a sidewall of the first gate electrode, a second gate spacer being formed on a sidewall of the second gate electrode and an interlayer insulating film covering the first gate spacer and the second gate spacer.
    Type: Application
    Filed: July 21, 2016
    Publication date: April 27, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sun-Ki Min, Gi-Gwan PARK, Sang-Koo KANG, Sung-Sao KIM, Ju-Youn KIM, Koung-Min RYU, Jae-Hoon LEE, Tae-Won HA
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20170110576
    Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.
    Type: Application
    Filed: October 11, 2016
    Publication date: April 20, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-Soo KIM, Gi-Gwan PARK, Sang-Koo KANG, Koung-Min RYU, Jae-Hoon LEE, Tae-Won HA
  • Stepped electrode assembly having predetermined a thickness ratio in the interface between electrode units, battery cell and device comprising the same
    Patent number: 9627708
    Abstract: There are provided an electrode assembly, and a battery cell, a battery pack, and a device. The electrode assembly includes a combination of two or more types of electrode units having different areas, wherein the electrode units are stacked such that steps are formed, and electrode units are formed such that a positive electrode and a negative electrode face one another at an interface between the electrode units.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: April 18, 2017
    Assignee: LG Chem, Ltd.
    Inventors: Sung-Jin Kwon, Soon-Ho Ahn, Dong-Myung Kim, Ki-Woong Kim, Young-Hoon Kim, Sung-Han Yoon, Seung-Min Ryu
  • Semiconductor device including redundancy cell array
    Patent number: 9601216
    Abstract: Provided is a semiconductor device and a manufacturing method thereof. The semiconductor device may include a first cell array, a first fuse circuit, a first spare cell array, a second spare cell array, and a redundancy select controller. The first fuse circuit may be configured to store a first failed address corresponding to one or more defective memory cells in the first cell array. Each of the first and second spare cell arrays may include a plurality of spare memory cells configured to replace first and second defective memory cells in the first cell array, respectively. For replacing the first and second defective memory cells, the redundancy select controller may be configured to selectively assign the first fuse circuit to either one or both of the first and second spare cell arrays.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: March 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-Min Ryu, Ho-Young Song, Yun-Young Lee
  • SEMICONDUCTOR DEVICE
    Publication number: 20170054020
    Abstract: A semiconductor device is provided that includes a deep trench defining an active region, and a fin-type pattern protruding within the active region. The fin-type pattern having a lower portion, an upper portion of a narrower width than the lower portion, and a first stepped portion formed at a boundary between the upper portion and the lower portion. The device also includes a first field insulating film surrounding the lower portion and a second field insulating film formed on the first field insulating film and partially surrounding the upper portion.
    Type: Application
    Filed: June 22, 2016
    Publication date: February 23, 2017
    Inventors: Sung-soo KIM, Koung-Min RYU, Sun-Ki Min
  • SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING GATE PROFILE USING THIN FILM STRESS IN GATE LAST PROCESS
    Publication number: 20170053913
    Abstract: There is provided a semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer using a hybrid interlayer insulating film. The semiconductor device includes a gate electrode on a substrate, a gate spacer being on a sidewall of the gate electrode and including an upper portion and a lower portion, a lower interlayer insulating film being on the substrate and overlapping with the lower portion of the gate spacer, and an upper interlayer insulating film being on the lower interlayer insulating film and overlapping with the upper portion of the gate spacer, wherein the lower interlayer insulating film is not interposed between the upper interlayer insulating film and the upper portion of the gate spacer.
    Type: Application
    Filed: August 10, 2016
    Publication date: February 23, 2017
    Inventors: Sun-Ki MIN, Koung-Min RYU, Sang-Koo KANG
  • APPARATUS FOR DEPOSITING A THIN FILM
    Publication number: 20170037537
    Abstract: An apparatus is provided for depositing a thin film. The apparatus includes a chamber, a susceptor disposed in the chamber and supporting a substrate, a reflection housing disposed outside the chamber, a light source unit disposed in the reflection housing and irradiating light to the susceptor, and a light controlling unit blocking at least a portion of an irradiation path of the light to control an irradiation area of the light on the susceptor. At least a portion of the light controlling unit is disposed in the reflection housing.
    Type: Application
    Filed: July 7, 2016
    Publication date: February 9, 2017
    Inventors: Seung-Min RYU, Sang Min LEE, HEE JONG JEONG, CHAEHO KIM, Ji Su SON, JAEBONG LEE, JUWAN LIM, JUNGWOO CHOI