Abstract: An operation method of a semiconductor memory device including a memory cell array and an internal processor configured to perform an internal processing operation includes receiving at the memory device a first mode indicator that indicates whether the memory device should operate in a processor mode or in a normal mode, receiving at the memory device processing information for the memory device, when the first mode indicator indicates that the memory device should operate in the processor mode, storing the processing information in a first memory cell region of the memory cell array, using the stored processing information to perform internal processing by the internal processor, and storing a result of the internal processing in the memory cell array.

Abstract: A method for treating a substrate includes a mixing step of preparing an ozone treatment fluid containing an ozone gas and a substrate treating step of treating a surface of the substrate using the ozone treatment fluid. In the substrate treating step, light is irradiated to the substrate by a lamp.

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

Abstract: The present invention provides a strain of Pseudozyma churashimaensis RGJ1, which is isolated from a pepper plant and leads to induced systemic resistance against plant pathogens or plant viruses; a microbial preparation for controlling plant diseases or increasing plant yields, including, as an active ingredient, the strain or a culture thereof; a method for preparing the microbial preparation, including a step of culturing the strain; and a method for controlling plant diseases, including a step of performing dipping treatment, soil drenching treatment or spraying treatment onto aerial foliage for a plant seedling with the strain or the culture thereof.

Abstract: A chuck pin, method for manufacturing a chuck pin, and an apparatus for treating substrate. The substrate treating apparatus includes a container having a treating space in its inner side, a supporting unit supporting the substrate inside of the treating space, and a liquid supply unit providing a solution to the supported substrate of the supporting unit. The supporting unit is placed in a supporting plate where the substrate is placed and in the above supporting plate, and includes a chuck pin supporting a side part of the substrate. The chuck pin is formed on a body and on the above surface of the body, and includes a first coating film provided as a silicon carbide material.

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

Abstract: A gas injector includes first and second gas introduction passages extending in a first direction toward a central axis of a process chamber respectively, a first bypass passage extending from the first gas introduction passage in a second direction that is substantially perpendicular to the first direction, a second bypass passage extending from the second gas introduction passage in a reverse direction to the second direction, a first distribution passage isolated from the first bypass passage in the first direction and extending from an outlet of the first bypass passage in the reverse direction to the second direction, a second distribution passage isolated from the second bypass passage in the first direction and extending from an outlet of the second bypass passage in the second direction, and a plurality of spray holes in an outer surface of the first and second distribution passages and configured to spray the process gas.

Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively, forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region, forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid, and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.

Abstract: A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.

Abstract: A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

Abstract: Disclosed is a method of preparing a solid electrolyte, the method including (a) preparing a solid electrolyte precursor by subjecting a mixed solution composed of a lanthanum precursor, a zirconium precursor, a gallium precursor, a complexing agent, and a pH adjuster to coprecipitation, (b) washing and drying the solid electrolyte precursor, (c) preparing a mixture by mixing the washed and dried solid electrolyte precursor with a lithium source, and (d) calcining the mixture to give a calcined solid electrolyte, which is a gallium (Ga)-doped lithium lanthanum zirconium oxide (LLZO), as represented by Chemical Formula 1. A solid electrolyte having increased ionic conductivity and an improved potential window can be provided using the method of preparing the solid electrolyte.

Abstract: A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.

Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively, forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region, forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid, and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.

Abstract: A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.

Abstract: A light-emitting element disclosed in an embodiment comprises: a body having a cavity; first and second lead frames arranged in the cavity; a third lead frame arranged between the first and second lead frames in the cavity; a fourth lead frame arranged between the first and second lead frames and distanced from the third frame in the cavity; a first light-emitting chip arranged on the first lead frame; and a second light-emitting chip arranged on the second lead frame, wherein the body comprises: first and second sides arranged on opposing sides from each other; and third and fourth sides arranged on opposing sides from each other, the first lead frame comprises first and second lead parts protruding toward the first and second sides, the second lead frame comprises third and forth lead parts protruding toward the first and second sides, the third frame comprises a fifth lead part protruding toward the first side, and the fourth lead frame comprises a sixth lead part protruding toward the second side.

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.