Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

Abstract: Provided is a semiconductor device including chip identification (ID) generation circuits. The semiconductor device may be a multi-chip package including a plurality of memory chips, and each of the memory chips includes a chip ID generation circuit configured to selectively modify a chip ID of a corresponding memory chip. The chip ID generation circuit determines the chip ID of the memory chip by testing the chip ID of the memory chip by using a mode register, and selectively programs the chip ID of the memory chip by using at least two fuse sets. The chip ID generation circuit may block an output of the chip ID of the memory chip when the memory chip is determined as a defective chip or is selected to stop its use.

Abstract: The present disclosure provides a hand grippable inside handle. Some forms of the present disclosure may include an upper grip handle and a lower grip handle which are coupled to an inner side of a door of a vehicle, a grip type inside handle having an upper portion engaged with the upper grip handle and a lower portion engaged with the lower grip handle, and an inside handle rod installed inside the grip type inside handle and configured to pivot with the grip type inside handle about an axis in a length direction when the grip type inside handle is pivoted, thereby operating a latch device of the door.

Abstract: A tin compound, tin precursor compound for atomic layer deposition (ALD), a method of forming a tin-containing material film, and a method of synthesizing a tin compound, the tin compound being represented by Chemical Formula (I): wherein R1, R2, Q1, Q2, Q3, and Q4 are each independently a C1 to C4 linear or branched alkyl group.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

Abstract: Disclosed are an apparatus for forming a layer and a method of forming the layer using the same. The apparatus includes a transfer chamber in which a substrate is transferred, a deposition chamber positioned at a side of the transfer chamber and performing a deposition process on the substrate to thereby form the layer on the substrate, and at least a de-hydrogen chamber positioned at another side of the transfer chamber and performing a de-hydrogen process on the layer on the substrate to reduce a hydrogen concentration in the layer. Accordingly, the de-hydrogen process is performed in the apparatus without unloading of the substrate from the apparatus.

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

Abstract: A tantalum compound, a method of forming a thin film, and a method of fabricating an integrated circuit device, the tantalum compound being represented by the following General Formula (I):

Abstract: A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.

Abstract: An apparatus is provided for depositing a thin film. The apparatus includes a chamber, a susceptor disposed in the chamber and supporting a substrate, a reflection housing disposed outside the chamber, a light source unit disposed in the reflection housing and irradiating light to the susceptor, and a light controlling unit blocking at least a portion of an irradiation path of the light to control an irradiation area of the light on the susceptor. At least a portion of the light controlling unit is disposed in the reflection housing.

Abstract: A semiconductor device is provided which includes a first fin-type pattern including a first side surface and a second side surface opposite to each other, a first trench of a first depth adjacent to the first side surface, a second trench of a second depth adjacent to the second side surface. The second depth differs from the first depth, and a first field insulating film partially fills the first trench and a second field insulating film partially fills the second trench. The first fin-type pattern has a lower portion, and an upper portion having a narrower width than the lower portion, and has a first stepped portion on a boundary between the upper portion and the lower portion. The first field insulating film includes a first lower field insulating film in contact with the lower portion, and a first upper field insulating film in contact with the upper portion.

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

Abstract: A tantalum compound, a method of forming a thin film, and a method of fabricating an integrated circuit device, the tantalum compound being represented by the following General Formula (I):

Abstract: An integrated circuit device includes a fin-type active area extending on a substrate in a first direction, a first gate line and a second gate line extending on the fin-type active area in parallel to each other in a second direction, which is different from the first direction, a first insulating capping layer covering an upper surface of the first gate line and extending in parallel to the first gate line, a second insulating capping layer covering an upper surface of the second gate line and extending in parallel to the second gate line, wherein a height of the first gate line and a height of the second gate line are different from each other.

Abstract: A semiconductor device includes a substrate including first to third regions, wherein the third region is positioned in a first direction between the first and second regions, a fin protruding on the substrate and extending in the first direction, first and second gate structures respectively formed on the fin in the first and second regions, first and second spacers formed with spacing apart from each other on the fin in the third region. The first and second spacers are sloped in a direction away from each other, and the first and second spacers and an upper surface of the fin define a plurality of acute angles, the first and second spacers defining a recess, the fin and the first and second spacers defining sidewalls of the recess, and a device isolating film substantially filling the recess.

Abstract: Disclosed is a bipolar all solid-state battery, which can efficiently control a manufacturing process thereof and can improve electric properties thereof. In an exemplary embodiment, the bipolar all solid-state battery includes a unit cell including a first current collector having a first surface and a second surface opposite to the first surface; a first active material coated on the first surface of the first current collector, a second current collector having a first surface and a second surface opposite to the first surface; a second active material coated on the first surface of the second current collector and facing the first active material; and an all solid-state electrolyte formed between the first active material and the second active material. When a plurality of the unit cells are stacked, the first current collector and the second current collector are connected to each other through surface contact.

Abstract: A semiconductor device is provided that includes a deep trench defining an active region, and a fin-type pattern protruding within the active region. The fin-type pattern having a lower portion, an upper portion of a narrower width than the lower portion, and a first stepped portion formed at a boundary between the upper portion and the lower portion. The device also includes a first field insulating film surrounding the lower portion and a second field insulating film formed on the first field insulating film and partially surrounding the upper portion.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.