Patents by Inventor Min Ying

Min Ying has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367535
    Abstract: In some embodiments, the present disclosure relates to a method for forming an integrated chip (IC), including forming a plurality of image sensing elements including a first doping type within a substrate, performing a first removal process to form deep trenches within the substrate, the deep trenches separating the plurality of image sensing elements from one another, performing an epitaxial growth process to form an isolation epitaxial precursor including a first material within the deep trenches and to form a light absorbing layer including a second material different than the first material within the deep trenches and between sidewalls of the isolation epitaxial precursor, performing a dopant activation process on the light absorbing layer and the isolation epitaxial precursor to form a doped isolation layer including a second doping type opposite the first doping type, and filling remaining portions of the deep trenches with an isolation filler structure.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 17, 2022
    Inventors: Yu-Hung Cheng, Ching I Li, Yu-Siang Fang, Yu-Yao Hsia, Min-Ying Tsai
  • Publication number: 20220320154
    Abstract: The present disclosure relates to an image sensor having an epitaxial deposited photodiode structure surrounded by an isolation structure, and an associated method of formation. In some embodiments, a first epitaxial deposition process is performed to form a first doped EPI layer over a substrate. The first doped EPI layer is of a first doping type. Then, a second epitaxial deposition process is performed to form a second doped EPI layer on the first doped EPI layer. The second doped EPI layer is of a second doping type opposite from the first doping type. Then, an isolation structure is formed to separate the first doped EPI layer and the second doped EPI layer as a plurality of photodiode structures within a plurality of pixel regions. The plurality of photodiode structures is configured to convert radiation that enters from a first side of the image sensor into an electrical signal.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 6, 2022
    Inventors: Min-Ying Tsai, Ching I Li
  • Publication number: 20220310691
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a through substrate via (TSV) in a first substrate. The TSV continuously extends from a first surface of the first substrate to a second surface of the first substrate. A conductive contact is formed on the second surface of the first substrate. The conductive contact comprises a first conductive layer disposed on the TSV. An upper conductive layer is formed between the conductive contact and the TSV. The upper conductive layer comprises a silicide of a conductive material of the first conductive layer.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 29, 2022
    Inventors: Min-Ying Tsai, Cheng-Ta Wu, Yeur-Luen Tu
  • Patent number: 11398516
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first through substrate via (TSV) disposed within a semiconductor substrate. The semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the semiconductor substrate. The semiconductor substrate comprises a first doped channel region extending from the front-side surface to the back-side surface. The first TSV is defined at least by the first doped channel region. A conductive contact overlies the back-side surface of the semiconductor substrate and comprises a first conductive layer overlying the first TSV. The first conductive layer comprises a conductive material. An upper conductive layer underlies the conductive contact. An upper surface of the upper conductive layer is aligned with the back-side surface of the semiconductor substrate. The upper conductive layer comprises a silicide of the conductive material.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Ying Tsai, Cheng-Ta Wu, Yeur-Luen Tu
  • Publication number: 20220130888
    Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 28, 2022
    Inventors: Cheng-Hsien Chou, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Hsiao-Hui Tseng, Min-Ying Tsai
  • Publication number: 20220123031
    Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 21, 2022
    Inventors: Min-Ying Tsai, Cheng-Te Lee, Rei-Lin Chu, Ching I Li, Chung-Yi Yu
  • Patent number: 11295222
    Abstract: A machine failure analyzing system includes a wearable electronic device is for a user to wear, a controlling and processing device provided with a machine history database and a failure causes analyzing unit. When a specific machine is malfunctioning or in a failure status, the controlling and processing device utilizes a machine status data collecting unit to collect machine status data from the specific machine. Subsequently, based on the machine status data, the failure causes analyzing unit is configured to find relative failure causes from the machine history database, thereby generating at least one troubleshooting solution. As such, under instructions of the troubleshooting solution, a field engineer who wears the wearable electronic device can achieve troubleshooting of the specific machine rapidly and precisely, without needing to spend time finding the failure causes.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: April 5, 2022
    Assignee: WE JUMP INTELLIGENT PERCEPTION CO., LTD.
    Inventors: Min-Ying Lin, Po-Shih Chiang
  • Patent number: 11291387
    Abstract: A system for recognizing abnormal activity of human body using wearable electronic device and mixed reality technology, includes a first wearable electronic device, a plurality of second wearable electronic devices, at least one camera, and a judgement module. The system is suitable to be applied in any type of work environment, so as to monitor and determine whether a user (i.e., an operator or an employee) exhibits abnormal activities by referring a document of standard operating procedures (SOP), an operating manual and a document of safety operation standard (SOS), to reduce a rate of user mishandling, thereby achieving the enhancement of work efficiency and productivity.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: April 5, 2022
    Assignee: We Jump Intelligent Perception Co., Ltd.
    Inventors: Ching-Han Chen, Min-Ying Lin, Po-Shih Chiang
  • Patent number: 11232975
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) substrate without bond interface voids and/or without delamination between layers. In some embodiments, a first high ? bonding structure is formed over a handle substrate. A device layer is formed over a sacrificial substrate. Outer most sidewalls of the device layer are between outer most sidewalls of the sacrificial substrate. A second high ? bonding structure is formed over the device layer. The first high ? bonding structure is bonded to the second high ? bonding structure, such that the device layer is between the sacrificial substrate and the handle substrate. A first removal process is performed to remove the sacrificial substrate. The first removal process comprises performing a first etch into the sacrificial substrate until the device layer is reached.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Ying Tsai, Yeur-Luen Tu
  • Patent number: 11217621
    Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Hsiao-Hui Tseng, Min-Ying Tsai
  • Publication number: 20210375962
    Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
    Type: Application
    Filed: August 12, 2021
    Publication date: December 2, 2021
    Inventors: CHIH-YU LAI, MIN-YING TSAI, YEUR-LUEN TU, HAI-DANG TRINH, CHENG-YUAN TSAI
  • Patent number: 11171039
    Abstract: A composite semiconductor substrate includes a semiconductor substrate, an oxygen-doped crystalline semiconductor layer and an insulative layer. The oxygen-doped crystalline semiconductor layer is over the semiconductor substrate, and the oxygen-doped crystalline semiconductor layer includes a crystalline semiconductor material and a plurality of oxygen dopants. The insulative layer is over the oxygen-doped crystalline semiconductor layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Min-Ying Tsai, Cheng-Ta Wu, Yu-Hung Cheng, Yeur-Luen Tu
  • Publication number: 20210335861
    Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.
    Type: Application
    Filed: September 11, 2020
    Publication date: October 28, 2021
    Inventors: Yu-Hung Cheng, Chun-Tsung Kuo, Jiech-Fun Lu, Min-Ying Tsai, Chiao-Chun Hsu, Ching I Li
  • Publication number: 20210298644
    Abstract: Disclosures of the present invention describe a system for recognizing abnormal activity of human body using wearable electronic device and mixed reality technology, comprising: a first wearable electronic device, a plurality of second wearable electronic devices, at least one camera, and a judgement module. This novel system is suitable for applying in any kinds of work environment, so as to monitor and determine whether a user (i.e., an operator or an employee) exhibits abnormal activities by referring a document of standard operating procedures (SOP), an operating manual and a document of safety operation standard (SOS), such that it is facilitated to reduce a happening rate of the user's mishandling, thereby achieving the enhancement of work efficiency and productivity.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Inventor: Min-Ying Lin
  • Patent number: 11101307
    Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Lai, Min-Ying Tsai, Yeur-Luen Tu, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Publication number: 20210229068
    Abstract: This invention relates to a dispersion comprising porous particles dispersed in a liquid phase, wherein the porous particles comprise a zeolite and the liquid phase is a size-excluded liquid. The invention also relates to a method of adsorbing a gas into a liquid, comprising at least the step of bringing the gas into contact with the dispersion. In addition, the invention relates to an assemblage of the dispersion, the zeolite comprising a cavity and a gas contained within the cavity.
    Type: Application
    Filed: November 1, 2018
    Publication date: July 29, 2021
    Inventors: Stuart JAMES, Min Ying TSANG, John CAHIR
  • Patent number: 11069733
    Abstract: In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Shyh-Fann Ting, Yen-Ting Chiang, Yeur-Luen Tu, Min-Ying Tsai
  • Patent number: D949427
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: April 19, 2022
    Inventor: Min Ying
  • Patent number: D956249
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: June 28, 2022
    Inventor: Min Ying
  • Patent number: D961799
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: August 23, 2022
    Inventor: Min Ying