Abstract: A semiconductor device includes an extended drain finFET. The drain drift region of the finFET extends between a drain contact region and a body of the finFET. The drain drift region includes an enhanced portion of the drain drift region between the drain contact region and the body. The drain drift region also includes a first charge balance region and a second charge balance region laterally adjacent to, and on opposite sides of, the enhanced portion of the drain drift region. The enhanced portion of the drain drift region and the drain contact region have a first conductivity type; the body, the first charge balance region, and the second charge balance region have a second, opposite, conductivity type. The drain drift region is wider than the body.

Abstract: A semiconductor package carrier board structure includes a plurality of carrier board bodies and a plurality of supporting bumps. The carrier board body includes a build-up circuit structure and a plurality of conductive blocks bonded to the build-up circuit structure. Adjacent ones of the carrier board bodies are connected to each other with their corresponding conductive blocks. An area formed by the adjacent conductive blocks defines a cutting path. An opening is formed on a surface of each of the conductive blocks at the cutting path. The supporting bumps are erected between the adjacent openings. As such, each of the supporting bumps corresponds to a position overlapping the cutting path to provide the support function of the semiconductor package carrier board structure when performing the semiconductor packaging operation. After performing the singulation operation, the supporting bumps can be completely removed and one side of the openings can be exposed.

Abstract: A method of manufacturing an electronic device includes providing a substrate, providing an intermediate layer on the substrate, and providing an isolation layer on the intermediate layer. The substrate includes an active region and a peripheral region. The peripheral region is adjacent to the active region, and the ratio of the area of the active region to the area of the substrate surface is between 75% and 92%. The isolation layer includes a first surface and at least one slope. The first surface of the isolation layer is correspondingly disposed in the active region. The at least one slope of the isolation layer is correspondingly disposed in the peripheral region and at a first angle with respect to the substrate surface.

Abstract: The embodiment of the disclosure provides a composite layer circuit element of an electronic device. The composite layer circuit element includes a first dielectric layer, a first circuit layer and a second dielectric layer. The first circuit layer is disposed on the first dielectric layer, and the second dielectric layer is disposed on the first circuit layer. A thickness of the first dielectric layer is greater than a thickness of the second dielectric layer in a cross section view.

Abstract: A word line driving circuit includes a first circuit and a second circuit. The first circuit is configured to provide a first word line driving voltage and a second word line driving voltage based on a first control signal, a second control signal, a first bias voltage, a second bias voltage and a base voltage. The second circuit is configured to provide the first control signal and the second control signal based on a third control signal, a fourth control signal, a word line control signal, a reverse word line control signal, the first bias voltage, the second bias voltage and the base voltage. The first bias voltage and the second bias voltage have different levels during the read mode and the program mode for adaptively adjusting the read voltage and the program voltage, thereby improving the data access time.

Abstract: A portable radio is provided that performs an impedance measurement to determine a radio frequency (RF) load type connected to an antenna port of the portable radio. The portable radio includes an impedance measurement circuit and a tunable matching circuit operatively coupled thereto through an RF switch A sweep generator injects an LMR frequency sweep to the RF load during non-transmit or non-receive time slots for the impedance measurement. The tunable matching circuit is configured as a radio frequency (RF) bypass during the impedance measurement, thereby enabling the impedance measurement circuit to directly measure the impedance of the RF load coupled to the RF port and identify the RF load as either a land mobile radio (LMR) antenna or equipment (wideband load). When the RF load is determined to be an LMR antenna, then the matching circuitry is tuned for the identified antenna. When the RF load is determined to be wideband equipment, then the matching circuitry remains bypassed.

Abstract: An antenna apparatus and a control method are provided. The antenna apparatus includes a first antenna, a second antenna, and a movable mechanism. The first antenna is operated on a first frequency band. The second antenna surrounds the first antenna and is operated on a second frequency band. The first and second antennas are disposed on the movable mechanism. The movable mechanism is further configured to steer a direction of the first and second antennas. Accordingly, the requirements of multiple frequency bands and beam scanning may be fulfilled.

Abstract: A method of fabricating a transistor includes forming a gate structure over a semiconductor substrate having a first conductivity type. A photoresist layer is patterned over the gate structure to remove the photoresist layer from over an uncovered portion of the gate structure and an adjacent region of the semiconductor substrate abutting the uncovered portion of the gate structure. A deep well region having the first conductivity type is formed using a first dopant such that the first dopant penetrates through the uncovered portion of the gate structure and is blocked by the photoresist layer. A shallow well region is formed by implanting a second dopant such that the second dopant penetrates the adjacent region and is blocked by the uncovered portion of the gate structure.

Abstract: The present invention relates to a composition of subunit dengue vaccine comprising a fusion protein of conjugating or connecting delta C nonstructural protein 1 (NS1?C or truncated NS1?C) to at least one polypeptides of NS3c (or truncated NS3c) and/or consensus envelope protein domain III (cEDIII), thereby enhancing better protection against DENV challenge and alleviating associated pathological effects.

Abstract: The embodiment of the disclosure provides a composite layer circuit element and a manufacturing method thereof. The manufacturing method of the composite layer circuit element includes the following. A carrier is provided. A first dielectric layer is formed on the carrier, and the first dielectric layer is patterned. The carrier on which the first dielectric layer is formed is disposed on a first curved-surface mold, and the first dielectric layer is cured. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is patterned. The carrier on which the first dielectric layer and the second dielectric layer are formed is disposed on a second curved-surface mold, and the second dielectric layer is cured. A thickness of a projection of the first curved-surface mold is smaller than a thickness of a projection of the second curved-surface mold.

Abstract: A display device is provided. The display device includes a substrate, a light-shielding layer, a plurality of first light-emitting elements, and a plurality of second light-emitting elements. The light-shielding layer is disposed on the substrate. The first light-emitting elements are disposed on the substrate. The second light-emitting elements are disposed between the light-shielding layer and the substrate. One of the second light-emitting elements is alternately disposed between any two adjacent first light-emitting elements.

Abstract: A device, system and method for routing botnet calls to a botnet call-answer queue. A device, such as a call answering point (CAP) and/or a public-safety answering point (PSAP) router device, receives a call and determines an audio signature of the call. The device compares the audio signature of the call with one or more botnet audio signatures stored at a memory. In response to the audio signature of the call matching at least one of the one or more botnet audio signatures, the device: identifies the call as a botnet call that has been placed by a botnet; and cause the call to be routed to a botnet call-answer queue.

Abstract: A method for processing a semiconductor wafer is provided. The method includes polishing the semiconductor wafer with a chemical mechanical polishing (CMP) tool. The method includes transferring the polished semiconductor wafer to an interface tool from the CMP tool. The method includes discharging a mist spray over the polished semiconductor wafer in the interface tool. The method includes transferring the semiconductor wafer form the interface tool to a cleaning tool for a cleaning process.

Abstract: The present disclosure generally relates to a bird's beak profile of a field oxide region. In an example, a semiconductor device structure includes a semiconductor substrate, a dielectric oxide layer, and a field oxide region. The semiconductor substrate has a top surface. The dielectric oxide layer is over the top surface of the semiconductor substrate. The field oxide region is over the semiconductor substrate. The field oxide region is connected to the dielectric oxide layer through a bird's beak region. A lower surface of the bird's beak region interfaces with the semiconductor substrate. In a cross-section along a direction from the field oxide region to the dielectric oxide layer, the lower surface of the bird's beak region does not have a slope with a magnitude that exceeds 0.57735, where rise of the slope is in a direction normal to the top surface of the semiconductor substrate.

Abstract: A fin field effect transistor (FinFET) includes a drain region, a merged drift region, and a plurality of fins. The drain region extends above a surface of a semiconductor substrate and has a first dopant concentration of first conductivity type. The merged drift region extends above the substrate surface and touches the drain region, and has a second lower dopant concentration of the first conductivity type. The plurality of fins extend above the substrate surface and each fin is directly connected to the merged drift region. Each fin is connected to a source region having the first conductivity type at a distal end of that fin from the merged drift region.

Abstract: The present disclosure generally relates to isolation of a semiconductor device formed in a semiconductor substrate. In an example, a semiconductor device includes a drift well, a drain region, a first dopant isolation region, and a second dopant isolation region. The drift well, drain region, first dopant isolation region, and second dopant isolation region are disposed in a semiconductor substrate. The drift well, drain region, and second dopant isolation region are doped with a first dopant conductivity type. The first dopant isolation region is doped with a second dopant conductivity type opposite from the first dopant conductivity type. The drain region is disposed within the drift well. The first dopant isolation region circumscribes the drain region. The first dopant isolation region is an electrically floating node. The second dopant isolation region circumscribes the first dopant isolation region.

Abstract: A method of preparing a self-healing composition is disclosed, the method including following steps. An isocyanate solution, a dihydric alcohol solution, and a metal salt solution are provided. The dihydric alcohol has heterocyclic structures. The isocyanate solution and the dihydric alcohol solution are mixed, causing the isocyanate and the dihydric alcohol polymerize to form a polymer precursor. The polymer precursor includes a hard segment and a soft segment. The hard segment includes urethane groups, the soft segment includes heterocyclic structures. The polymer precursor and the metal salt solution are mixed, causing the heterocyclic structures and metal ions to undergo a chelation reaction to form a coordination complex, thereby forming the self-healing composition. A self-healing composition prepared by the method, and self-healing film using the self-healing composition are also disclosed.

Abstract: A manufacturing method of a package structure of an electronic device, including the following steps, is provided. A first seed layer is formed on a carrier plate. A first metal layer is formed on the first seed layer. A first insulating layer is formed on the first metal layer, wherein the first insulating layer exposes a portion of the first metal layer. A first plasma treatment is performed on the first insulating layer and the exposed portion of the first metal layer. After performing the first plasma treatment, the carrier plate formed with the first seed layer, the first metal layer, and the first insulating layer is placed in a microenvironment controlling box. After taking the carrier plate out of the microenvironment controlling box, a second seed layer is formed on the first insulating layer and the exposed portion of the first metal layer.

Abstract: The present disclosure introduces a microelectronic device including a source side field plate in a microelectronic device. The microelectronic device may be configured as a metal oxide semiconductor (MOS) transistor, a laterally diffused metal oxide semiconductor (LDMOS) transistor, a drain extended metal oxide semiconductor (DEMOS) transistor, a bipolar junction transistor, a junction field effect transistor, a CMOS transistor, or a gated bipolar device. The source side field plate extends over the source region by a distance which is more than a quarter of the width of the source region. Transistors may suffer from Vt shifts during gate and drain stress over time. The source side field plate reduces the electric field of the transistor near the gate electrode corner on the source side of the transistor. The gate injection current on the source side and electron trapping in the gate oxide thereby reduced which reduces Vt shifts over time.

Abstract: A system for performing a chemical mechanical polishing (CMP) process is provided. The system includes a CMP tool configured to polish a semiconductor wafer. The processing system further includes a wafer stage configured to support the semiconductor wafer for facilitating the insertion of the semiconductor wafer into, and its subsequent removal from, the CMP tool. The processing system also includes a number of spray nozzles positioned relative to the wafer stage. In addition, the processing system includes a spray generator connected to the spray nozzles and configured to convert a mixture to a mist spray. The processing system further includes a controller configured to activate flow of the mist spray from the spray generator to the spray nozzles to discharge the mist spray over the semiconductor wafer supported by the wafer stage.