Abstract: A fin field-effect transistor (“FinFET”) semiconductor device and method of forming the same. In one example, a semiconductor fin is formed over a semiconductor substrate. A conformal dielectric layer is formed on a top and side surfaces of the fin. A doped semiconductor layer is formed over the conformal dielectric layer, the doped semiconductor layer including a dopant. The doped semiconductor layer is heated thereby driving the dopant through the conformal dielectric layer and forming a doped region of the fin.

Abstract: A word line driving circuit includes a first circuit and a second circuit. The first circuit is configured to provide a first word line driving voltage and a second word line driving voltage based on a first control signal, a second control signal, a first bias voltage, a second bias voltage and a base voltage. The second circuit is configured to provide the first control signal and the second control signal based on a third control signal, a fourth control signal, a word line control signal, a reverse word line control signal, the first bias voltage, the second bias voltage and the base voltage. The first bias voltage and the second bias voltage have different levels during the read mode and the program mode for adaptively adjusting the read voltage and the program voltage, thereby improving the data access time.

Abstract: A fin field effect transistor (FinFET) includes a drain region, a merged drift region, and a plurality of fins. The drain region extends above a surface of a semiconductor substrate and has a first dopant concentration of first conductivity type. The merged drift region extends above the substrate surface and touches the drain region, and has a second lower dopant concentration of the first conductivity type. The plurality of fins extend above the substrate surface and each fin is directly connected to the merged drift region. Each fin is connected to a source region having the first conductivity type at a distal end of that fin from the merged drift region.

Abstract: An integrated circuit including a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, and a body region. The source region includes an outer region having a first conductivity type complementary to a second conductivity type of an outer region of the body and an interior-positioned conductive region having the second conductivity type.

Abstract: An integrated circuit (IC) having a fin field effect transistor (FinFET) includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, a drift region, and field plating oxide layer. The drift region is adjacent the drain region. The field plating oxide layer is on a first side, a second side, and a third side of the drift region.

Abstract: One example includes an integrated circuit (IC) comprising a fin field effect transistor (FinFET). The FinFET includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, and a drift region adjacent the drain region. The fin also includes a field-plating (FP) dielectric layer on a first side, a second side, and a third side of the drift region. The FP dielectric layer includes a high-K material.

Abstract: A package device is provided and includes a first circuit layer, a first isolation layer, and a first de-warpage layer. The first circuit layer and the first isolation layer are stacked on each other. At least a portion of the first de-warpage layer is disposed between the first circuit layer and the first isolation layer.

Abstract: The embodiment of the disclosure provides a composite layer circuit element and a manufacturing method thereof. The manufacturing method of the composite layer circuit element includes the following. A carrier is provided. A first dielectric layer is formed on the carrier, and the first dielectric layer is patterned. The carrier on which the first dielectric layer is formed is disposed on a first curved-surface mold, and the first dielectric layer is cured. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is patterned. The carrier on which the first dielectric layer and the second dielectric layer are formed is disposed on a second curved-surface mold, and the second dielectric layer is cured. A thickness of a projection of the first curved-surface mold is smaller than a thickness of a projection of the second curved-surface mold.

Abstract: The invention provides a paper cup holder with carrying handles, comprising a first base board, a first wall board, a surface board, a second wall board and a second base board located on one extension line, connected sequentially, and forming a tubular structure. The first and second base boards overlap with each other and jointly serve as a bottom surface of the tubular structure. The first base board is partially connected with the surface board to increase a load capacity of the paper cup holder. The surface board is provided with two carrying handle forming line sets and at least two cup inlet forming lines. The surface board forms two carrying handles based on the two carrying handle forming line sets and forms two hollow areas, and each of the two hollow areas and at least one of the cup inlet forming lines jointly form a cup inlet.

Abstract: The invention provides a paper cup holder with carrying handles, comprising a first base board, a first wall board, a surface board, a second wall board and a second base board located on one extension line, connected sequentially, and forming a tubular structure. The first and second base boards overlap with each other and jointly serve as a bottom surface of the tubular structure. The first base board is partially connected with the surface board to increase a load capacity of the paper cup holder. The surface board is provided with two carrying handle forming line sets and at least two cup inlet forming lines. The surface board forms two carrying handles based on the two carrying handle forming line sets and forms two hollow areas, and each of the two hollow areas and at least one of the cup inlet forming lines jointly form a cup inlet.

Abstract: A method for fabricating an integrated circuit is disclosed. The method comprises forming a semiconductor ridge over a semiconductor surface of a substrate and forming an implant screen on a top and sidewalls of the semiconductor ridge. The implant screen is at least two times thicker on the top of the semiconductor ridge relative to the sidewalls of the semiconductor ridge. The method further comprises implanting a dopant into the top and sidewalls of the semiconductor ridge.

Abstract: A method and apparatus for writing a report is described herein. During the process an officer will acquire an image of an incident scene. The image may comprise a live image, a video, or a still image (picture). Potential objects of interest will be highlighted within the image for selection by the officer. When an object of interest is selected (e.g., touched on a touch screen), a description of the object of interest will be inserted at a point in a report where a cursor lies. The user will also be allowed to transcribe (via speech to text) their report, and have text representing their speech inserted where the cursor lies.

Abstract: An integrated circuit (IC) having a fin field effect transistor (FinFET) includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, a drift region, and field plating oxide layer. The drift region is adjacent the drain region. The field plating oxide layer is on a first side, a second side, and a third side of the drift region.

Abstract: A method for forming a layer includes following operations. A workpiece is received in an apparatus for deposition. The apparatus for deposition includes a chamber, a pedestal disposed in the chamber to accommodate the workpiece, and a ring disposed on the pedestal. The ring includes a ring body having a first top surface and a second top surface and a barrier structure disposed between the first top surface and the second top surface. A vertical distance is defined by a top surface of the barrier structure and a top surface of the workpiece. The vertical distance is between approximately 0 mm and approximately 50 mm. A target disposed in the apparatus for deposition is sputtered. A sputtered material is deposited onto a top surface of the workpiece to form a layer. The barrier structure alters an electrical density distribution during the depositing the sputter material.

Abstract: A computing device obtains a video and obtains a target facial image, where the target facial image comprises a target face to be edited. The computing device determines a target facial feature vector from the target facial image to be edited. For each of a plurality of frames in the video, the computing device is further configured to: identify facial regions of individuals depicted in the video, generate candidate facial feature vectors for each of the identified facial regions, compare each of the candidate facial feature vectors to the target facial feature vector, and apply a mask effect to facial regions of corresponding facial feature vectors based on the comparison to generate an edited video.

Abstract: A fingerprint identification apparatus, including a light path adjustment element, an optical filter layer, and an image sensor, is provided. The light path adjustment element is disposed on a transmission path of an image beam from a fingerprint of a user. The optical filter layer is disposed on a transmission path of the image beam from the light path adjustment element. The optical filter layer has openings. An inclined image beam in the image beam is obliquely incident to the light path adjustment element. The light path adjustment element adjusts a light path of the inclined image beam to be transmitted to the openings along a normal direction. The image sensor is disposed on a transmission path of the image beam from the optical filter layer. The image sensor has pixels. Positions of the pixels respectively correspond to positions of the openings.

Abstract: A method for fabricating an integrated circuit is disclosed. The method comprises forming a semiconductor ridge over a semiconductor surface of a substrate and forming an implant screen on a top and sidewalls of the semiconductor ridge. The implant screen is at least two times thicker on the top of the semiconductor ridge relative to the sidewalls of the semiconductor ridge. The method further comprises implanting a dopant into the top and sidewalls of the semiconductor ridge.

Abstract: A computing device obtains a video, generates a user interface displaying a plurality of facial effects, and obtains selection of one or more facial effects displayed in the user interface. A target facial image is obtained, where the target facial image comprises a target face to be edited. The computing device determines a target facial feature vector from the target facial image to be edited. For each of a plurality of frames in the video, the computing device identifies facial regions of individuals depicted in the video, generates candidate facial feature vectors for each of the identified facial regions, compares each of the candidate facial feature vectors to the target facial feature vector, and applies one or more facial effects to facial regions based on the comparison to generate an edited video.

Abstract: A redistribution layer structure and the manufacturing method thereof are provided. The redistribution layer structure includes a first metal layer, a first dielectric layer, a second metal layer, and a second dielectric layer. The first dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the second metal layer. A chemical resistance of the first dielectric layer is greater than a chemical resistance of the second dielectric layer.

Abstract: A fin field effect transistor (FinFET) includes a drain region, a merged drift region, and a plurality of fins. The drain region extends above a surface of a semiconductor substrate and has a first dopant concentration of first conductivity type. The merged drift region extends above the substrate surface and touches the drain region, and has a second lower dopant concentration of the first conductivity type. The plurality of fins extend above the substrate surface and each fin is directly connected to the merged drift region. Each fin is connected to a source region having the first conductivity type at a distal end of that fin from the merged drift region.