Patents by Inventor Nan Fang

Nan Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11282772
    Abstract: A package structure includes at least one electronic device, a protection layer and an encapsulant. The electronic device has a first surface and includes a plurality of bumps disposed adjacent to the first surface thereof. Each of the bumps has a first surface. The protection layer covers the bumps and the first surface of the electronic device, and has a first surface. The encapsulant covers the protection layer and at least a portion of the electronic device, and has a first surface. The first surfaces of the bumps, the first surface of the protection layer and the first surface of the encapsulant are substantially coplanar with each other.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: March 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Patent number: 11276661
    Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a first wiring structure and at least one electronic device. The at least one electronic device is connected to the first wiring structure through at least two joint structures. The at least two joint structures respectively include different materials.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Publication number: 20220059406
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes disposing a first semiconductor substrate on a temporary carrier and dicing the first semiconductor substrate to form a plurality of dies. Each of the plurality of dies has an active surface and a backside surface opposite to the active surface. The backside surface is in contact with the temporary carrier and the active surface faces downward. The method also includes transferring one of the plurality of dies from the temporary carrier to a temporary holder. The temporary holder only contacts a periphery portion of the active surface of the one of the plurality of dies.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsu-Nan FANG
  • Patent number: 11257788
    Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: February 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Patent number: 11257776
    Abstract: A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Sheng Lin, Chin-Li Kao, Hsu-Nan Fang
  • Patent number: 11248262
    Abstract: The invention refers to a novel method of preparing strand-specific RNA-sequencing libraries that can be used to identify DNA coding and non-coding strands that are transcribed to RNA. Such strand-specific RNA-sequencing libraries are especially useful in discovering anti-sense RNA and non-coding RNA. Random primer oligonucleotides, covalently coupled to a moiety, which blocks ligation, are used for RT reaction or the subsequent generation of the second DNA strand so that only one strand of the generated double-stranded DNA is ligated to sequencing adapters at the 5? nucleotide and sequenced by paired-end sequencing.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: February 15, 2022
    Assignee: QIAGEN GmbH
    Inventors: Nan Fang, Bernhard Noll, Katja Heitz
  • Patent number: 11217498
    Abstract: A semiconductor package includes a semiconductor die having a first surface and a second surface opposite to the first surface, a conductive wiring layer stacked with the semiconductor die and proximal to the first surface, an encapsulant encapsulating the semiconductor die and stacked with the conductive wiring layer, and a replacement structure exposing from the encapsulant and being free of fillers. A method for manufacturing the semiconductor package is also disclosed in the present disclosure.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: January 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chien-Ching Chen, Chen Yuan Weng
  • Patent number: 11211319
    Abstract: A device structure includes a first electronic structure and a plurality of first electric contacts. The first electronic structure has a surface and a center. The first electric contacts are exposed from the surface. The first electric contacts are spaced by a pitch that increases with increasing distance from the center.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Chen Yuan Weng
  • Patent number: 11195771
    Abstract: A substrate structure includes a substrate, an encapsulating layer and a redistribution structure. The substrate has a first surface. The encapsulating layer surrounds the substrate and has a first surface. The redistribution structure is disposed on the first surface of the substrate and the first surface of the encapsulating layer. A gap exists in elevation between the first surface of the substrate and the first surface of the encapsulating layer.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: December 7, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Publication number: 20210366864
    Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a first wiring structure and at least one electronic device. The at least one electronic device is connected to the first wiring structure through at least two joint structures. The at least two joint structures respectively include different materials.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsu-Nan FANG
  • Publication number: 20210327819
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Patent number: 11139268
    Abstract: A semiconductor package structure includes a substrate, a first semiconductor die, a first dielectric, a second semiconductor die, and a second dielectric. The substrate has a first surface. The first semiconductor die is disposed on the first surface. The first dielectric encapsulates the first semiconductor die. The second semiconductor die is disposed on the first surface and adjacent to the first semiconductor die. The second dielectric encapsulates the second semiconductor die. The first dielectric is in contact with the second dielectric. An average filler size in the first dielectric is substantially greater than an average filler size in the second dielectric.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Patent number: 11139252
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh
  • Patent number: 11133284
    Abstract: A semiconductor package device includes a circuit layer, a first set of stacked components, a first conductive wire, a space and an electronic component. The first set of stacked components is disposed on the circuit layer. The first conductive wire electrically connects the first set of stacked components. The space is defined between the first set of stacked components and the circuit layer. The space accommodates the first conductive wire. The electronic component is disposed in the space.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: September 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Jen-Hsien Wong
  • Publication number: 20210225737
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first semiconductor element, a first redistribution layer, a second redistribution layer, and a conductive via. The first semiconductor element has a first active surface and a first back surface opposite to the first active surface. The first redistribution layer is disposed adjacent to the first back surface of the first semiconductor element. The second redistribution layer is disposed adjacent to the first active surface of the first semiconductor element. The conductive via is disposed between the first redistribution layer and the second redistribution layer, where the conductive via inclines inwardly from the second redistribution layer to the first redistribution layer.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsu-Nan FANG
  • Publication number: 20210193578
    Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Publication number: 20210175163
    Abstract: A semiconductor device package includes a redistribution structure, a conductive substrate stacked on the redistribution structure and an encapsulant encapsulating the redistribution structure and the conductive substrate. The encapsulant encapsulates a side surface of the conductive substrate. A method for manufacturing an electronic device package includes: providing a carrier, forming a redistribution structure on the carrier, mounting a conductive substrate on a first surface of the redistribution structure, forming a first encapsulant to encapsulate the first surface of the redistribution structure and a side surface of the conductive substrate, and removing the carrier.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 10, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsu-Nan FANG
  • Publication number: 20210175139
    Abstract: A substrate structure includes a substrate, an encapsulating layer and a redistribution structure. The substrate has a first surface. The encapsulating layer surrounds the substrate and has a first surface. The redistribution structure is disposed on the first surface of the substrate and the first surface of the encapsulating layer. A gap exists in elevation between the first surface of the substrate and the first surface of the encapsulating layer.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 10, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsu-Nan FANG
  • Patent number: 11024838
    Abstract: A production method of a negative electrode active material for non-aqueous electrolyte secondary batteries containing particles of lithium-containing silicon compound includes: preparing particles of silicon compound containing a silicon compound (SiOx: 0.5?x?1.6); obtaining particles of lithium-containing silicon compound by making the particle of silicon compound contact with a solution A that contains lithium and has an ether-based solvent as a solvent; and heating the particles of the lithium-containing silicon compound. A production method of a negative electrode active material for non-aqueous electrolyte secondary batteries is capable of increasing battery capacity of the negative electrode active material and capable of improving the first time efficiency and cycle characteristics.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 1, 2021
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hiromichi Kamo, Takakazu Hirose, Katsunori Nishiura, Nan Fang
  • Publication number: 20210159188
    Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device, a protection material and a reinforcement structure. The first electronic device and the second electronic device are electrically connected to the wiring structure. The protection material is disposed between the first electronic device and the wiring structure and between the second electronic device and the wiring structure. The reinforcement structure is disposed on and contacts the first electronic device and the second electronic device. The reinforcement structure contacts the protection material.
    Type: Application
    Filed: November 22, 2019
    Publication date: May 27, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Yung-I YEH