Patents by Inventor Naoki Shibata

Naoki Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030155575
    Abstract: An AlN buffer layer 2; a silicon (Si)-doped GaN high-carrier-concentration n+ layer 3; an Si-doped n-type Al0.07Ga0.93N n-cladding layer 4; an Si-doped n-type GaN n-guide layer 5; an active layer 6 having a multiple quantum well (MQW) structure, and including a Ga0.9In0.1N well layer 61 (thickness: about 2 nm) and a Ga0.97In0.03N barrier layer 62 (thickness: about 4 nm), the layers 61 and 62 being laminated alternately; an Mg-doped GaN p-guide layer 7; an Mg-doped Al0.07Ga0.93N p-cladding layer 8; and an Mg-doped GaN p-contact layer 9 are successively formed on a sapphire substrate. A p-electrode 10 is formed of a film of titanium nitride (TiN) or tantalum nitride (TaN) (thickness: 50 nm). The contact resistance of this electrode is reduced through heat treatment.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 21, 2003
    Inventors: Naoki Shibata, Toshiya Uemura, Makoto Asai, Yasuo Koide, Masanori Murakami
  • Publication number: 20030153112
    Abstract: A method for manufacturing a light-emitting device which using group III nitride group semiconductors and a quantum well structure, comprising forming a well layer (e.g. an InGaN layer), forming a cap layer on the well layer, the cap layer having almost the same compositions as the well layer at a temperature similar to that at which the well layer was formed. Further, and the cap layer is formed at a crystal growth rate which is faster than the crystal growth rate of the well layer and removing the cap layer using a thermal cracking (or decomposition) process during the temperature ramp up associated with the formation of the next group III nitride compound semiconductor layer. After the cap layer is removed, the group III nitride compound semiconductor layer is formed on the exposed well layer.
    Type: Application
    Filed: February 27, 2003
    Publication date: August 14, 2003
    Inventors: Hiroshi Watanabe, Naoki Shibata
  • Publication number: 20030134447
    Abstract: A titanium layer and a titanium nitride layer are successively laminated on a substrate and a group III nitride compound semiconductor layer is further formed thereon. When the titanium layer is removed in the condition that a sufficient film thickness is given to the titanium nitride layer, a device having the titanium nitride layer as a substrate is obtained.
    Type: Application
    Filed: December 11, 2002
    Publication date: July 17, 2003
    Inventors: Naoki Shibata, Masanobu Senda
  • Patent number: 6593016
    Abstract: A group III nitride compound semiconductor device has a substrate and an AlN single crystal layer formed on the substrate. The AlN single crystal layer has a thickness of from 0.5 to 3 &mgr;m and has a substantially flat surface. The half-value width of an X-ray rocking curve of the AlN single crystal layer is not longer than 50 sec. In another device, a group III nitride compound semiconductor layer having a thickness of from 0.01 to 3.2 &mgr;m is grown at a temperature of from 1000 to 1180° C. on a sapphire substrate having a surface nitride layer having a thickness of not larger than 300 Å.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: July 15, 2003
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiaki Chiyo, Naoki Shibata, Masanobu Senda, Jun Ito, Shizuyo Asami, Shinya Asami, Hiroshi Watanabe
  • Patent number: 6589808
    Abstract: A GaN type semiconductor layer having a new structure is provided which incorporates a substrate having surface which is opposite to a GaN type semiconductor layer and which is made of Ti.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: July 8, 2003
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiaki Chiyo, Shizuyo Noiri, Naoki Shibata, Jun Ito
  • Publication number: 20030122251
    Abstract: A LED has a thin highly resistive or insulative layer formed below an electrode pad in order to divert current flow from the region below an electrode pad, which region does not contribute to light emission, to another region which does. Consequently, better current efficiency is obtained. Further, diverting current flow from the region below the electrode pad where mechanical damages are expected deters deterioration of the region. Consequently, the LED lasts longer and is a better quality product.
    Type: Application
    Filed: February 24, 2003
    Publication date: July 3, 2003
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Makoto Asai
  • Publication number: 20030109076
    Abstract: A preferred condition for forming a Group III nitride compound semiconductor layer on a substrate by a sputtering method is proposed. When a first Group III nitride compound semiconductor layer is formed on a substrate by a sputtering method, an initial voltage of a sputtering apparatus is selected to be not higher than 110% of a sputtering voltage.
    Type: Application
    Filed: October 21, 2002
    Publication date: June 12, 2003
    Inventors: Masanobu Senda, Jun Ito, Toshiaki Chiyo, Naoki Shibata, Shizuyo Asami
  • Patent number: 6573117
    Abstract: A layer comprising cobalt (Co) is formed on a p+ layer by vapor deposition, and a layer comprising gold (Au) is formed thereon. The two layers are alloyed by a heat treatment to form a light-transmitting electrode. The light-transmitting electrode therefore has reduced contact resistance and improved light transmission properties, and gives a light-emitting pattern which is stable over a long time. Furthermore, since cobalt (Co) is an element having a large work function, satisfactory ohmic properties are obtained.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: June 3, 2003
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Naoki Shibata, Shizuyo Noiri, Masanori Murakami, Yasuo Koide, Jun Ito
  • Patent number: 6573114
    Abstract: A LED has a thin highly resistive or insulative layer formed below an electrode pad in order to divert current flow from the region below an electrode pad, which region does not contribute to light emission, to another region which does. Consequently, better current efficiency is obtained. Further, diverting current flow from the region below the electrode pad where mechanical damages are expected deters deterioration of the region. Consequently, the LED lasts longer and is a better quality product.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: June 3, 2003
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Makoto Asai
  • Patent number: 6562646
    Abstract: A method for manufacturing a light-emitting device which using group III nitride group semiconductors and a quantum well structure, comprising forming a well layer (e.g. an InGaN layer), forming a cap layer on the well layer, the cap layer having almost the same compositions as the well layer at a temperature similar to that at which the well layer was formed. Further, and the cap layer is formed at a crystal growth rate which is faster than the crystal growth rate of the well layer and removing the cap layer using a thermal cracking (or decomposition) process during the temperature ramp up associated with the formation of the next group III nitride compound semiconductor layer. After the cap layer is removed, the group III nitride compound semiconductor layer is formed on the exposed well layer.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: May 13, 2003
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Hiroshi Watanabe, Naoki Shibata
  • Publication number: 20030085411
    Abstract: A group III nitride compound semiconductor device has a substrate, a group III nitride compound semiconductor layer having a device function, and an undercoat layer formed between the substrate and the group III nitride semiconductor layer. The undercoat layer has a surface which has a texture structure, or which is trapezoid shaped in section or which is pit shaped. In addition, a reflection layer made of nitride of at least one metal selected from the group consisting of titanium, zirconium, hafnium and tantalum may be formed on a surface of the undercoat layer. Also the surface of the reflection layer is formed as a texture structure, a trapezoid shape in section or a pit shape.
    Type: Application
    Filed: November 26, 2002
    Publication date: May 8, 2003
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Naoki Shibata, Toshiaki Chiyo, Masanobu Senda, Jun Ito, Hiroshi Watanabe, Shinya Asami, Shizuyo Asami
  • Patent number: 6531719
    Abstract: A group III nitride compound semiconductor device has a substrate, a group III nitride compound semiconductor layer having a device function, and an undercoat layer formed between the substrate and the group III nitride semiconductor layer. The undercoat layer has a surface which has a texture structure, or which is trapezoid shaped in section or which is pit shaped. In addition, a reflection layer made of nitride of at least one metal selected from the group consisting of titanium, zirconium, hafnium and tantalum may be formed on a surface of the undercoat layer. Also the surface of the reflection layer is formed as a texture structure, a trapezoid shape in section or a pit shape.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: March 11, 2003
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Toshiaki Chiyo, Masanobu Senda, Jun Ito, Hiroshi Watanabe, Shinya Asami, Shizuyo Asami
  • Publication number: 20030042505
    Abstract: An undercoat layer inclusive of a metal nitride layer is formed on a substrate. Group III nitride compound semiconductor layers are formed on the undercoat layer continuously.
    Type: Application
    Filed: December 18, 2001
    Publication date: March 6, 2003
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Jun Ito, Toshiaki Chiyo, Naoki Shibata, Hiroshi Watanabe, Shizuyo Asami, Shinya Asami
  • Publication number: 20030006430
    Abstract: A photo-excited semiconductor layer smaller in band gap energy than a light-emitting layer made of a Group III nitride compound semiconductor is provided between a substrate and the light-emitting layer. The photo-excited semiconductor layer is excited by the light emitted from the light-emitting layer to thereby emit light at a wavelength longer than that of the light emitted from the light-emitting layer.
    Type: Application
    Filed: June 7, 2002
    Publication date: January 9, 2003
    Inventors: Naoki Shibata, Takahiro Kozawa
  • Publication number: 20030001170
    Abstract: Disclosed is a Group III nitride compound semiconductor light-emitting element formed of Group III nitride compound semiconductor layers, including a multi-layer containing light-emitting layers; a p-type semiconductor layer; and an n-type semiconductor layer, wherein the multi-layer includes a multiple quantum barrier-well layer containing quantum-barrier-formation barrier layers formed from a Group III nitride compound semiconductor and quantum-barrier-formation well layers formed from a Group III nitride compound semiconductor, the barrier layers and the well layers being laminated alternately and cyclically, and a plurality of low-energy-band-gap layers which emit light of different wavelengths; and the multiple quantum barrier-well layer is provided between the low-energy-band-gap layers.
    Type: Application
    Filed: June 6, 2002
    Publication date: January 2, 2003
    Inventors: Naoki Shibata, Takahiro Kozawa, Kazuyoshi Tomita, Tetsu Kachi
  • Patent number: 6500689
    Abstract: A layer comprising cobalt (Co) is formed on a p+ layer by vapor deposition, and a layer comprising gold (Au) is formed thereon. The two layers are alloyed by a heat treatment to form a light-transmitting electrode. The light-transmitting electrode therefore has reduced contact resistance and improved light transmission properties, and gives a light-emitting pattern which is stable over a long time. Furthermore, since cobalt (Co) is an element having a large work function, satisfactory ohmic properties are obtained.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: December 31, 2002
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Naoki Shibata, Shizuyo Noiri, Masanori Murakami, Yasuo Koide, Jun Ito
  • Patent number: 6426512
    Abstract: An undercoat layer inclusive of a metal nitride layer is formed on a substrate. Group III nitride compound semiconductor layers are formed on the undercoat layer continuously.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: July 30, 2002
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Jun Ito, Toshiaki Chiyo, Naoki Shibata, Hiroshi Watanabe, Shizuyo Asami, Shinya Asami
  • Publication number: 20020070383
    Abstract: A group III nitride compound semiconductor device is produced according to the following manner. A separation layer made of a material which prevents group III nitride compound semiconductors from being grown thereon is formed on a substrate. Group III nitride compound semiconductors is grown on a surface of the substrate uncovered with the separation layer while keeping the uncovered substrate surface separated by the separation layer.
    Type: Application
    Filed: November 6, 2001
    Publication date: June 13, 2002
    Inventors: Naoki Shibata, Jun Ito, Toshiaki Chiyo, Shizuyo Asami, Hiroshi Watanabe, Shinya Asami
  • Patent number: D471340
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: March 4, 2003
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Naoki Shibata, Takafumi Nakatani, Masafumi Abe
  • Patent number: D471689
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: March 11, 2003
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Naoki Shibata, Takafumi Nakatani, Masafumi Abe