Patents by Inventor Ning Chen

Ning Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11139432
    Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Miao Liu, Bwo-Ning Chen, Kei-Wei Chen
  • Patent number: 11139540
    Abstract: The present disclosure relates to a battery module and a battery pack. The battery module comprises two or more secondary batteries arranged side by side in a first direction, each of which includes a case, an electrode assembly and a closing portion, wherein the case has a receiving hole comprising an opening and extending in a second direction, and the first direction intersects with the second direction, wherein the closing portion is sealingly connected with the case to close the opening, the electrode assembly is disposed in the receiving hole and includes two or more electrode units, the electrode unit includes a first electrode plate, a second electrode plate and a separator, and the two or more electrode units are stacked in the second direction.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 5, 2021
    Assignee: Contemporary Amperex Technology Co., Limited
    Inventors: Haizu Jin, Dongyang Shi, Zhenhua Li, Xingdi Chen, Ning Chen, Fei Hu
  • Patent number: 11133386
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The structure includes a semiconductor substrate; a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; and a gate stack disposed over the fin.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bwo-Ning Chen, Xusheng Wu, Chang-Miao Liu
  • Patent number: 11124780
    Abstract: The present disclosure relates to a genetically engineered strain with high production of uridine and its construction method and application. The strain was constructed as follows: heterologously expressing pyrimidine nucleoside operon sequence pyrBCAKDFE (SEQ ID NO:1) on the genome of E coli prompted by strong promoter Ptrc to reconstruct the pathway of uridine synthesis; overexpressing the autologous prsA gene coding PRPP synthase by integration of another copy of prsA gene promoted by strong promoter Ptrc on the genome; deficiency of uridine kinase, uridine phosphorylase, ribonucleoside hydrolase, homoserine dehydrogenase I and ornithine carbamoyltransferase. When the bacteria was used for producing uridine, 40-67 g/L uridine could be obtained in a 5 L fermentor after fermentation for 40-70 h using the technical scheme provided by the disclosure with the maximum productivity of 0.15-0.25 g uridine/g glucose and 1.
    Type: Grant
    Filed: May 12, 2019
    Date of Patent: September 21, 2021
    Assignee: Tianjin University of Science and Technology
    Inventors: Xixian Xie, Ning Chen, Heyun Wu, Guoliang Li, Qiang Li, Xiaoguang Fan, Qingyang Xu, Chenglin Zhang, Yanjun Li, Qian Ma
  • Publication number: 20210283598
    Abstract: Described herein are multi-well separation devices configured to allow a composition comprising a target agent to be separated into multiple wells, subdivided, recombined into a single well, and/or re-separated into the same or a different configuration of wells. Also described herein are reagent loading devices configured to simultaneously deliver one or more test agents to a plurality of volumes without having to individually deliver the test agents. Together, these devices allow high throughput parallel processes without repetitive pipetting or liquid handling robotics, though they may also be used separately. Also described herein are kits and systems for chemical or biological assays, as well as methods for using the multi-well separation devices and reagent loading devices described herein.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Applicant: DrugArray, Inc.
    Inventors: Ning CHEN, Robert Keith SHANAHAN, Dayu TENG, Daniel Joseph BRAUN
  • Publication number: 20210271544
    Abstract: First data is received. First error-checking data generated based on a cyclic redundancy check (CRC) operation of the first data is received. Second data is generated by combining the first data with a first data pattern. Second error-checking data of the second data is generated by using a combination of the first error-checking data and a second data pattern. The second data pattern has a size that is based on the first data pattern.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 2, 2021
    Inventors: Ning Chen, Juane Li
  • Patent number: 11096939
    Abstract: Provided herein are KRAS G12C inhibitors, such as composition of the same, and methods of using the same. These inhibitors are useful for treating a number of disorders, including pancreatic, colorectal, and lung cancers.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 24, 2021
    Assignee: Amgen Inc.
    Inventors: Shon Booker, John Gordon Allen, Brian Alan Lanman, Ryan Paul Wurz, Ning Chen, Victor J. Cee, Patricia Lopez, Aaron C. Siegmund, Michael D. Bartberger
  • Patent number: 11092483
    Abstract: A light sensor with high linearity is provided. A photoelectric component converts light energy into a photocurrent to a first capacitor. An error amplifier has a first amplification input terminal and a second amplification input terminal, which are respectively connected to a reference voltage source and a first terminal of a first transistor. A first terminal of a second transistor is connected to the second amplification input terminal. A second terminal of the first transistor is connected to the first capacitor. An output terminal of the error amplifier is connected to a second terminal of the second transistor. A first comparator compares a voltage of the first capacitor with a lowest one of a modulated voltage and a reference voltage to generate a first comparing signal. A counter circuit performs counting according to the first comparing signal.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: August 17, 2021
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventor: Chih-Ning Chen
  • Patent number: 11090304
    Abstract: Provided herein are KRAS G12C inhibitors, composition of the same, and methods of using the same. These inhibitors are useful for treating a number of disorders, including pancreatic, colorectal, and lung cancers.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: August 17, 2021
    Assignee: Amgen Inc.
    Inventors: John Gordon Allen, Jennifer Rebecca Allen, Ana Elena Minatti, Qiufen Xue, Ryan Paul Wurz, Christopher M. Tegley, Alexander J. Pickrell, Thomas T. Nguyen, Vu Van Ma, Patricia Lopez, Longbin Liu, David John Kopecky, Michael J. Frohn, Ning Chen, Jian Jeffrey Chen, Aaron C. Siegmund, Albert Amegadzie, Nuria A. Tamayo, Shon Booker, Clifford Goodman, Mary Walton, Nobuko Nishimura, Youngsook Shin, Jonathan D. Low, Victor J. Cee, Anthony B. Reed, Hui-Ling Wang, Brian Alan Lanman
  • Patent number: 11090654
    Abstract: Described herein are multi-well separation devices configured to allow a composition comprising a target agent to be separated into multiple wells, subdivided, recombined into a single well, and/or re-separated into the same or a different configuration of wells. Also described herein are reagent loading devices configured to simultaneously deliver one or more test agents to a plurality of volumes without having to individually deliver the test agents. Together, these devices allow high throughput parallel processes without repetitive pipetting or liquid handling robotics, though they may also be used separately. Also described herein are kits and systems for chemical or biological assays, as well as methods for using the multi-well separation devices and reagent loading devices described herein.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: August 17, 2021
    Assignee: DRUGARRAY, INC.
    Inventors: Ning Chen, Robert Keith Shanahan, Dayu Teng, Daniel Joseph Braun
  • Patent number: 11088560
    Abstract: A charger having a fast transient response and a control method thereof are provided, which decide how to quickly respond to a requirement of a load by determining whether an input current reference signal indicating an input current is larger than or equal to a maximum safe current of a transformer. Therefore, the charger and the control method realize the fast transient response without having to control switching between a boost circuit and a buck circuit. Meanwhile, the charger and the control method thereof can be prevented from being damaged by an excessive input current and can stabilize an output voltage of the load more quickly.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 10, 2021
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Chun-Kai Hsu, Chih-Ning Chen
  • Patent number: 11088423
    Abstract: The disclosure relates to a secondary battery and a battery module. The secondary battery comprises: a case comprising a receiving hole having an opening; a cap assembly connected with the case to close the opening; an electrode assembly disposed in the receiving hole, wherein the electrode assembly comprises two end surfaces opposite to each other in a first direction and tabs extending from respective end surfaces, and there are two or more electrode assemblies stacked in the axial direction; and a current collector comprising an extending portion and a current collecting portion connected to the tab, wherein the extending portion extends in the axial direction, the current collecting portion comprises a connecting end extending in a second direction perpendicular to both the axial direction and the first direction, and is connected to an end of the extending portion away from the cap assembly through the connecting end.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: August 10, 2021
    Assignee: Contemporary Amperex Technology Co., Limited
    Inventors: Haizu Jin, Dongyang Shi, Ning Chen, Zhenhua Li
  • Patent number: 11080132
    Abstract: A request to store a first data is received. The first data and a first error-checking data are received. The first error-checking data can be based on a cyclic redundancy check (CRC) operation of the first data. A second data is generated by removing a portion of the first data. A second error-checking data of the second data is generated by using the first error-checking data and the removed portion of the first data.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ning Chen, Juane Li
  • Patent number: 11081401
    Abstract: A method for manufacturing a semiconductor device, includes: forming a shallow trench isolation structure surrounding a first semiconductor fin and a second semiconductor fin; forming a dummy gate structure across the first and second semiconductor fins; forming a first flowable dielectric layer over the first and second semiconductor fins; curing the first flowable dielectric layer at a first temperature; removing a first portion of the cured first flowable dielectric layer from above the second semiconductor fin; after removing the first portion of the cured first flowable dielectric layer, forming a second flowable dielectric layer over the second semiconductor fin; curing the second flowable dielectric layer at a second temperature different from the first temperature; and replacing the dummy gate structure with a metal gate structure.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bwo-Ning Chen, Xu-Sheng Wu, Chang-Miao Liu
  • Publication number: 20210234044
    Abstract: A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.
    Type: Application
    Filed: July 28, 2020
    Publication date: July 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Winnie Victoria Wei Ning CHEN, Pang-Yen TSAI, Yasutoshi OKUNO
  • Patent number: 11069942
    Abstract: The present invention relates to a secondary battery and a battery module. The secondary battery includes: a casing including a receiving cavity having an opening; a top cover assembly, and an electrode assembly disposed in the receiving cavity, wherein the electrode assembly includes two end faces disposed opposite to each other in a first direction perpendicular to a depth direction of the receiving cavity, a lug extending from each end face; the lug is a layered structure and has a redundant section near the end face and a connecting section connected to the redundant section; the current collecting member includes a current collecting portion fixedly connected to the connecting section. The lug of the secondary battery of the embodiment of the present invention has the redundant section, which can effectively buffer the movement and reduce the possibility that the lug is torn or broken due to an excessive tensile stress.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 20, 2021
    Assignee: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Dongyang Shi, Yuanbao Chen, Haizu Jin, Zhenhua Li, Ning Chen, Fei Hu, Tian Wu
  • Patent number: 11068336
    Abstract: A request to store a first data is received. The first data and a first error-checking data are received. The first error-checking data can be based on a cyclic redundancy check (CRC) operation of the first data. A second data is generated by modifying the first data. A second error-checking data of the second data is generated by using the first error-checking data and a difference between the first data and the second data.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: July 20, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Ning Chen, Juane Li, Fangfang Zhu
  • Publication number: 20210207159
    Abstract: Stevia varieties with high a content of RebD, a high content of RebM, and a high content of RebD and RebM containing various SNP markers and UGT isoforms, are disclosed. Methods of screening for the SNPs are also disclosed as well as for using the SNPs in marker assisted breeding. Further provided are methods for introgressing the disclosed SNPs associated with high RebD and high RebM into stevia plants by selecting plants comprising for one or more SNPs and breeding with such plants to confer such desirable agronomic phenotypes to plant progeny.
    Type: Application
    Filed: March 18, 2021
    Publication date: July 8, 2021
    Applicant: PureCircle SDN BHD
    Inventors: Avetik Markosyan, Seong Siang Ong, Yeen Yee Wong, Yu Cheng Bu, Jian Ning Chen
  • Patent number: 11057384
    Abstract: The present disclosure relates to a method and system for updating a webpage and a webpage server. The method includes: upon detection of an update instruction, acquiring a feature value of an update process that generates the update instruction, the feature value comprising a process name and process identification of the update process; comparing the acquired feature value with each set of feature values in a preset process whitelist; and if there is an item in the preset process whitelist which is identical to the acquired feature value, adjusting a stored webpage document according to the update instruction.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: July 6, 2021
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventors: Zhijun Liu, Ning Chen
  • Publication number: 20210199501
    Abstract: A dynamical time gain controlling light sensing device generates a detection time configuration signal according to a light intensity indication signal, and generates a set of adjustment switch signals to respectively control the plurality of gain selection switches to be turned on or off according to a ratio of a real gain time and a simulation gain time within a detection time, such that an overall gain of a resolution adjustment circuit can correspond to an substitute gain lower than a set gain within the simulation gain time and correspond to the set gain within the real gain time, thereby generating an adjusted count result signal.
    Type: Application
    Filed: June 10, 2020
    Publication date: July 1, 2021
    Inventors: CHIH-NING CHEN, CHIH-HENG SU