Patents by Inventor Pei Yu

Pei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • VEHICLE DECORATIVE PLATE AND FORMING METHOD THEREOF
    Publication number: 20210122301
    Abstract: A vehicle decorative plate and a forming method thereof are disclosed. The vehicle decorative plate can be made into a vehicle emblem, a vehicle grille, a vehicle front bumper trim, a vehicle door trim or a vehicle rear bumper trim. The vehicle decorative plate includes a curved substrate, a display layer, and a curved covering. After the curved substrate is coated with a plating layer, unnecessary parts of the plating layer are removed by laser engraving to process the plating layer into the display layer. The curved covering is attached to the curved substrate and covers the display layer. At least one of the curved substrate and the curved covering is transparent or semi-transparent.
    Type: Application
    Filed: August 27, 2020
    Publication date: April 29, 2021
    Inventors: YI-KUAN LIN, PEI-YU WANG, FU-CHIEH HU
  • High-throughput cargo delivery into live cells using photothermal platforms
    Patent number: 10982217
    Abstract: Methods, devices, and systems are provided for the delivery of agents (e.g., nucleic acids, proteins, organic molecules, organelles, antibodies or other ligands, 5 etc.) into live cells and/or the extraction of the same from said cells. In various embodiments the photothermal platforms and systems incorporating such photothermal platforms are provided that permit efficient, high-throughput cargo delivery into live cells.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: April 20, 2021
    Assignee: The Regents of the University of California
    Inventors: Yi-Chien Wu, Ting-Hsiang S. Wu, Pei-Yu E. Chiou, Michael A. Teitell
  • Artificial joint
    Patent number: 10973647
    Abstract: An artificial joint includes a first joint assembly and a second joint assembly. The first joint assembly is adapted to be connected to a first bone and has a first contacting surface, wherein the first contacting surface includes a first convex arc surface, a second convex arc surface, and a third convex arc surface. The second joint assembly is adapted to be connected to a second bone and has a second contacting surface, wherein the second contacting surface is in contact with the first contacting surface and includes a first concave arc surface, a second concave arc surface, and a third concave arc surface, and the first concave arc surface, the second concave arc surface, and the third concave arc surface respectively correspond to the first convex arc surface, the second convex arc surface, and the third convex arc surface.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: April 13, 2021
    Assignees: Industrial Technology Research Institute, National Taiwan University Hospital
    Inventors: Pei-I Tsai, Hsin-Hsin Shen, Kuo-Yi Yang, De-Yau Lin, Yi-Hung Wen, Chih-Chieh Huang, Wei-Luan Fan, Pei-Yu Chen, Ching-Chi Hsu
  • Continuous whole-chip 3-dimensional DEP cell sorter and related fabrication method
    Patent number: 10967387
    Abstract: A 3-dimensional PDMS cell sorter having multiple passages in a PDMS layer that follow the same path in a DEP separation region and that are in fluid communication with each other within that region. The passages may differ in width transverse to the flow direction within the passages. Flat plates may sandwich the PDMS layer; each plate may have a planar electrode used to generate a DEP field within a sample fluid flowed within the passages. The DEP field may concentrate target cells or particulates within one of the passages within the DEP separation region. The passages may diverge after the DEP-separation region, leaving one passage with a high concentration of target cells or particulates. Techniques for manufacturing such structures, as well as other micro-fluidic structures, are also provided.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 6, 2021
    Assignee: The Regents of the University of California
    Inventors: Pei-Yu E. Chiou, Kuo-Wei Huang, Yu-Jui Fan, Yu-Chun Kung
  • SEMICONDUCTOR DEVICE AND METHODS OF FORMING THE SAME
    Publication number: 20210098365
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.
    Type: Application
    Filed: March 2, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Yu Chou, Jr-Hung Li, Liang-Yin Chen, Su-Hao Liu, Tze-Liang Lee, Meng-Han Chou, Kuo-Ju Chen, Huicheng Chang, Tsai-Jung Ho, Tzu-Yang Ho
  • Method and device for boosting performance of FinFETs via strained spacer
    Patent number: 10964816
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Chieh Yang, Li-Yang Chuang, Pei-Yu Wang, Wei Ju Lee, Ching-Wei Tsai, Kuan-Lun Cheng
  • FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210091191
    Abstract: A field effect transistor includes a semiconductor substrate, source and drain regions, lower source and drain contacts, a metal gate, a first interlayer dielectric layer, a capping layer, and an etch stop layer. The source and drain regions are disposed on the semiconductor substrate. The lower source and drain contacts are disposed on the source and drain regions. The metal gate is disposed in between the lower source and drain contacts. The first interlayer dielectric layer encircles the metal gate and the lower source and drain contacts. The capping layer is disposed on the metal gate. The etch stop layer extends on the first interlayer dielectric layer. An etching selectivity for the etch stop layer over the capping layer is greater than 10.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsai-Jung Ho, Jr-Hung Li, Tze-Liang Lee, Pei-Yu Chou, Chi-Ta Lee
  • Multi-Gate Device and Fabrication Methods Thereof
    Publication number: 20210091179
    Abstract: A semiconductor device includes a substrate, semiconductor wires disposed over the substrate, a gate structure wrapping around each of the semiconductor wires, and an epitaxial source/drain (S/D) feature in contact with the semiconductor wires. A portion of the epitaxial S/D feature is horizontally surrounded by an air gap.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Inventors: Pei-Yu Wang, Wei Ju Lee
  • Barrier-Free Interconnect Structure and Manufacturing Method Thereof
    Publication number: 20210082803
    Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Pei-Yu Wang, Cheng-Ting Chung, Wei Ju Lee
  • Methods of Forming Air Spacers in Semiconductor Devices
    Publication number: 20210083114
    Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Chao-Hsun Wang, Chen-Ming Lee, Kuo-Yi Chao, Mei-Yun Wang, Pei-Yu Chou, Kuo-Ju Chen
  • Method for cancer grading
    Patent number: 10948482
    Abstract: The invention relates to a method for establishing an index for a given cancer grade. The method includes profiling glycan distribution pattern of a reference cancer cell sample; adsorbing the profiled reference cancer cell sample with adsorbents; measuring the amount of the adsorbents adhering onto the profiled reference cancer cell sample; and acquiring reference correlations between the glycan distribution pattern of the reference cancer cell sample and the amount of the adsorbents adhering onto the profiled reference cancer cell sample to form the index of the given cancer grade. An index for a given cancer grade and a method for grading cancer of a test cell sample are also provided.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 16, 2021
    Assignee: NATIONAL SYNCHROTRON RADIATION RESEARCH CENTER
    Inventors: Yao-Chang Lee, Pei-Yu Huang
  • Method and apparatus for surface and ambient temperature estimation for portable devices
    Patent number: 10942067
    Abstract: The surface temperature of a portable device is estimated. The portable device includes a sensor for detecting the internal temperature of the portable device. The portable device also includes circuitry for estimating the surface temperature, using the internal temperature and an ambient temperature of the portable device as input to a circuit model. The circuit model describes thermal behaviors of the portable device. The circuitry is operative to identify a scenario in which the portable device operates, and determine the ambient temperature using the scenario and at least the internal temperature.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: March 9, 2021
    Assignee: MediaTek Inc.
    Inventors: Chi-Wen Pan, Pei-Yu Huang, Sheng-Liang Kuo, Jih-Ming Hsu, Tai-Yu Chen, Yun-Ching Li, Wei-Ting Wang
  • METAL OXIDE INTERLAYER STRUCTURE FOR nFET AND pFET
    Publication number: 20210066469
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.
    Type: Application
    Filed: June 8, 2020
    Publication date: March 4, 2021
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Runtime power table index adjustment for performance and power management
    Patent number: 10921876
    Abstract: Power and performance of a multi-core system is managed dynamically by adjusting power table indices at runtime. Runtime statistics is measured, when an application is executed on a first core of a first type at a first operating point (OPP) in a first time period, and on a second core of a second core type at a second OPP in a second time period. A controller estimates, based on the runtime statistics, a first pair of indices associated with a first OPP for the first core and a second pair of indices associated with a second OPP for the second core. During runtime, the controller incorporates the first pair of indices and the second pair of indices into power table indices; and determines, from the power table indices, selected indices associated with a selected OPP of a core of a selected core type for executing the application.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: February 16, 2021
    Assignee: MediaTek Inc.
    Inventors: Jih-Ming Hsu, Tai-Hua Lu, Pei-Yu Huang, Chien-Yuan Lai, Shu-Hsuan Chou, I-Cheng Cheng, Yun-Ching Li, Ming Hsien Lee
  • Projection system and keystone correction method
    Patent number: 10904501
    Abstract: A projection system and a keystone correction method are provided. The projection system includes: a projector projecting an image to a projection zone; an image capturing device capturing a captured image including the projection zone; and a processor. The processor divides the captured image into multiple focusing zones, and controls a stepper motor to shift focusing on the focusing zones at edges to obtain a step of the stepper motor and a distance for each of the focusing zones with a maximum clarity value. The distance is a projection distance between a lens module and the focusing zone. The processor calculates an included angle between the direction of a light axis of the projector and the projection zone according to the distances of the focusing zones at the edges, and performs a warping operation on a projection image according to the included angle.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: January 26, 2021
    Assignee: Coretronic Corporation
    Inventors: Yu-Chi Wu, Pei-Yu Li
  • Multi-flux microfluidic chip for nucleic acid detection and capable of actively controlling flow path, and use method thereof
    Patent number: 10875019
    Abstract: The present invention discloses a multi-flux microfluidic chip for nucleic acid detection and capable of actively controlling a flow path, and a use method thereof. The detection chip includes a chip body, and the chip body is provided with a sample loading chamber, a reaction chamber, and a microfluidic channel, where there is a plurality of reaction chambers, and the microfluidic channel includes a sample output main channel and several sample distribution channels.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 29, 2020
    Assignee: Lansion Biotechnology Co., Ltd.
    Inventors: Xingshang Xu, Jeffery Chen, Tao Zhu, Pei Yu
  • CONTROLLING ACCESS TO MICROSERVICES WITHIN A MULTI-TENANCY FRAMEWORK
    Publication number: 20200404021
    Abstract: In some examples, a system includes a network managed by a service provider and configured to provide access to one or more objects to a set of tenants each having one or more users, the service provider and the set of tenants being part of a set of entities that form a hierarchy, and a controller having access to the network. The controller is configured to obtain data indicative of a set of parameters, where the data indicative of the set of parameters is associated with an owner entity of the set of entities, generate a rule which incorporates the set of parameters, where the rule enables the controller to control access to an object of the one or more objects, and add the rule to a rules database, wherein the rules database is accessible to the controller.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Gurminder Singh, Pei-Yu Yang, Rong Xie
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20200388692
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Chun-Hsiung LIN, Chia-Hao CHANG, Chih-Hao WANG, Wai-Yi LIEN, Chih-Chao CHOU, Pei-Yu WANG
  • DEVICE FOR CONTINUOUS FOCUSING AND ROTATION OF BIOLOGICAL CELLS AND ITS USE FOR HIGH THROUGHPUT ELECTROROTATION FLOW CYTOMETERY
    Publication number: 20200386666
    Abstract: In certain embodiments a device is provided for electrorotation flow. In certain embodiments the device comprises a microfluidic channel comprising a plurality of electrodes disposed to provide dielectrophoretic (DEP) forces that are perpendicular to hydrodynamic flows along the channel; and a fluid within the channel providing the hydrodynamic flow along the channel; wherein the device is configured to apply focusing voltages to the electrodes that provide an electric field minimum in the channel and that focus cells, particles, and/or molecules or molecular complexes within the channel; and where the device is configured to apply rotation-inducing voltages to the electrodes that induce rotation of the cells, particles, molecules and/or molecular complexes as they flow through the channel.
    Type: Application
    Filed: April 5, 2018
    Publication date: December 10, 2020
    Inventors: Yu-Chun Kung, Tianxing Man, Pei-Yu E. Chiou
  • Wireless charging device
    Patent number: D901380
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 10, 2020
    Assignees: GOLDEN TSANN YUH ENTERPRISE CO., LTD., PEPIDEA CO., LTD.
    Inventors: Yi-Ling Tsai, Pei-Yu Wang, Pai-Feng Chen