Patents by Inventor Pei Yu

Pei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11532744
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, a gate cut feature extending continuously from between the first gate structure and the second gate structure to between the first backside dielectric feature and the second backside dielectric feature, and a liner disposed between the gate cut feature and the first backside dielectric feature and between the gate cut feature and the second backside dielectric feature.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220392876
    Abstract: A light-emitting device includes a first carrier, which includes a side surface between a first surface and a second surface, upper conductive pads on the first surface, and lower conductive pads under the second surface; a RDL pixel package includes a RDL which includes bonding pads and bottom electrodes, and the light-emitting units on the RDL, and connected to the bonding pads. A light-transmitting layer on the RDL and covers the light-emitting units, an upper surface, a lower surface, and a lateral surface between the upper surface and the lower surface. The RDL pixel package is on the first surface and electrically connected to the upper conductive pads. A protective layer covers the first surface and contacting the side surface of the RDL pixel package. The lower electrodes and the upper conductive pads are connected, and the distance between two adjacent bonding pads is less than 30 ?m.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 8, 2022
    Inventors: Min-Hsun HSIEH, Hsin-Mao LIU, Li-Yuan HUANG, Tzu-Hsiang WANG, Chi-Chih PU, Ya-Wen LIN, Hsiao-Pei CHIU, Pei-Yu LI
  • Publication number: 20220384602
    Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface, a first sidewall of the source epitaxial structure, and a second sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh SU, Li-Zhen YU, Chun-Yuan CHEN, Cheng-Chi CHUANG, Shang-Wen CHANG, Yi-Hsun CHIU, Pei-Yu WANG, Ching-Wei TSAI, Chih-Hao WANG
  • Publication number: 20220384590
    Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chuan Chiu, Huan-Chieh Su, Pei-Yu Wang, Cheng-Chi Chuang, Chun-Yuan Chen, Li-Zhen Yu, Chia-Hao Chang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20220384251
    Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: I-Ping LEE, Kwang-Ming LIN, Chih-Cherng LIAO, Ya-Huei KUO, Pei-Yu CHANG, Ya-Ting CHANG, Tsung-Hsiung LEE, Zheng-Xian WU, Kai-Chuan KAN, Yu-Jui CHANG, Yow-Shiuan LIU
  • Patent number: 11516254
    Abstract: In some examples, a system includes a network managed by a service provider and configured to provide access to one or more objects to a set of tenants each having one or more users, the service provider and the set of tenants being part of a set of entities that form a hierarchy, and a controller having access to the network. The controller is configured to obtain data indicative of a set of parameters, where the data indicative of the set of parameters is associated with an owner entity of the set of entities, generate a rule which incorporates the set of parameters, where the rule enables the controller to control access to an object of the one or more objects, and add the rule to a rules database, wherein the rules database is accessible to the controller.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: November 29, 2022
    Assignee: JUNIPER NETWORKS, INC.
    Inventors: Gurminder Singh, Pei-Yu Yang, Rong Xie
  • Patent number: 11516220
    Abstract: This disclosure is directed to devices, systems, and techniques for enforcing access to resources within a computer network. In some examples, a system includes a network managed by a service provider and configured to provide a plurality of microservices to a plurality of tenants each having one or more users and a controller having access to the network. The controller is configured to output, to a user interface, data indicative of a plurality of capabilities for presentation by the user interface and receive, from the user interface, data indicative of a user selection of a set of capabilities and a user selection of a new role identifier. The controller is further configured to create, based on the set of capabilities and the role identifier, a role which enables access to a set of actions within a computer network, the set of actions corresponding to the set of capabilities.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 29, 2022
    Assignee: JUNIPER NETWORKS, INC.
    Inventors: Gurminder Singh, Pei-Yu Yang, Rong Xie
  • Patent number: 11513810
    Abstract: A method of configuring a display device interface (DDI) detects a trigger signal, generated by a display device. If the trigger signal is associated with a power on event, a full configuration of the DDI is performed, including loading display device capability information provided by the display device into DDI configuration registers and setting one or more DDI configuration parameters accordingly. If the trigger signal is associated with resume event, rather than a power on event, a modified fast link resume operation may be performed to route the trigger signal to a controller configured to explicitly write display device capability information to the appropriate DDI configuration registers before setting the corresponding DDI configuration parameter accordingly. The DDI may include a re-timer, between the DDI source and sink, configured to snoop the explicit write transaction such that the re-timer configuration is also updated.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: November 29, 2022
    Assignee: Dell Products L.P.
    Inventors: Chung-Wei Wang, Chih-Chung Lin, You-Liang Chen, Pei-Yu Wang
  • Publication number: 20220366161
    Abstract: A device detecting system is provided. The device detecting system includes a bar code scanner, a plurality of device accommodating spaces, a screen, and a server. The server obtains bar code information via the bar code scanner and opens one of the device accommodating spaces based on the bar code information to accommodate an electronic device. The server performs a test procedure on the electronic device to generate a test result, and displays the test result and operation information corresponding to the test result on the screen.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 17, 2022
    Inventors: Chien-Chih CHANG, Pei-Yin CHEN, Wei-Han LIN, Bo-Rong CHU, Yen-Ting LIU, Yu-Shen MAI, Kuan-Yu HSIAO, Chia-Hsien LIN, Pei-Yu LIAO, Chun-Yen LAI, Sheng-Yi CHEN
  • Publication number: 20220355269
    Abstract: A method of treating or remediating contaminated material, such as water or soil, comprises contacting such material with asphaltenes. The asphaltenes are preferably produced as a by-product of petroleum refining and, in particular, a by-product of vacuum residua. An adsorbent material comprising such asphaltenes is also provided.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Applicant: Well Resources Inc.
    Inventors: Warren CHUNG, Xuebing LI, Pei YU, Mengtao CUI, Quan SHI, Zhiming XU, Suoqi ZHAO, Chunming XU, Keng H. CHUNG
  • Publication number: 20220359515
    Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.
    Type: Application
    Filed: May 6, 2021
    Publication date: November 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Yu CHOU, Yi-Ting FU, Ting-Gang CHEN, Tze-Liang LEE
  • Publication number: 20220359747
    Abstract: Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: CHUN-YUAN CHEN, HUAN-CHIEH SU, PEI-YU WANG, CHIH-HAO WANG
  • Publication number: 20220359396
    Abstract: In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Pei-Yu Wang, Yu-Xuan Huang
  • Publication number: 20220359711
    Abstract: A semiconductor device and method of manufacture which utilize isolation structures between semiconductor regions is provided. In embodiments different isolation structures are formed between different fins in different regions with different spacings. Some of the isolation structures are formed using flowable processes. The use of such isolation structures helps to prevent damage while also allowing for a reduction in spacing between different fins of the devices.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Pei Yu Lu, Je-Ming Kuo
  • Publication number: 20220352339
    Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.
    Type: Application
    Filed: July 7, 2022
    Publication date: November 3, 2022
    Inventor: Pei-Yu Wang
  • Publication number: 20220343205
    Abstract: A method for environment-specific training of a machine learning model, comprises receiving, for a local environment, a data stream including a plurality of sequential data snippets. Programmed labels are generated for each data snippet using a student version of a machine learning model. A portion of data snippets and associated programmed labels are selected and uploaded to a server-side computing device for evaluation by a teacher version of the machine learning model. An environment-specific training update is received from the server-side computing device. This training update is based on a comparison of the selected programmed labels and pseudolabels generated for the selected portion of data snippets by the teacher version. The environment-specific training update is applied to the student version to generate an updated student version. The updated student version of the machine learning model is then used to generate programmed labels for newly received data snippets.
    Type: Application
    Filed: April 21, 2021
    Publication date: October 27, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Pei YU, Zicheng LIU, Ying JIN, Yinpeng CHEN, Kun LUO
  • Publication number: 20220336449
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a source region, a drain region, and a gate electrode layer disposed between the source region and the drain region. The gate electrode layer includes a first surface facing the source region, and the first surface includes an edge portion having a first height. The gate electrode layer further includes a second surface opposite the first surface and facing the drain region. The second surface includes an edge portion having a second height. The second height is different from the first height.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Huan-Chieh SU, Chun-Yuan CHEN, Pei-Yu WANG, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20220336220
    Abstract: A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Inventors: Pei-Yu WANG, Zhi-Chang LIN, Ching-Wei TSAI, Kuan-Lun CHENG
  • Publication number: 20220310365
    Abstract: A plasma processing apparatus for semiconductor processing includes an injector holder configured to removably mate with a structure defining an interior chamber of a plasma processing apparatus. The injector holder defines a first opening. A sleeve is configured to be received within the first opening, and the sleeve defines a second opening. A gas injector is configured to be received within the second opening of the sleeve.
    Type: Application
    Filed: July 7, 2021
    Publication date: September 29, 2022
    Inventor: Pei-Yu LEE
  • Patent number: 11450751
    Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface and a first sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.
    Type: Grant
    Filed: January 24, 2021
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu, Pei-Yu Wang, Ching-Wei Tsai, Chih-Hao Wang