Abstract: A method of forming a strained vertical p-type field effect transistor, including forming a counter-doped layer at a surface of a substrate, forming a source/drain layer on the counter-doped layer, forming one or more vertical fins on the source/drain layer, removing a portion of the source/drain layer to form one or more bottom source/drains below each of the one or more vertical fins, reacting an exposed portion of each of the one or more bottom source/drains with a reactant to form a disposable layer on opposite sides of each bottom source/drain and a condensation layer between the two adjacent disposable layers, and removing the disposable layers.

Abstract: An ultra-small diameter and a tall bottom electrode for use in magnetic random access memory (MRAM) devices containing a multilayered MTJ pillar is provided. The bottom electrode is formed by depositing a thick bottom electrode layer on a surface of a metallic etch stop layer. The bottom electrode layer is then patterned by lithography and etching to provide a bottom electrode structure. An angled ion beam etch is thereafter used to trim the bottom electrode structure into a bottom electrode having a high aspect ratio (on the order of 10:1 or greater).

Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. The method first provides an electrically conductive structure embedded in an interconnect dielectric material layer of a magnetoresistive random access memory device. A conductive landing pad is located on a surface of the electrically conductive structure. A multilayered magnetic tunnel junction (MTJ) structure and an MTJ cap layer is formed on the landing pad. Then there is formed a first conductive layer on top the MTJ cap layer and a second conductive metal layer formed on top the first conductive layer. A pillar mask structure is then patterned and formed on the second conductive layer. The resulting structure is subject to lithographic patterning and etching to form a patterned bilayer metal hardmask pillar structure on top the MTJ cap layer. Subsequent etch processing forms an MTJ stack having sidewalls aligned to the patterned bilayer metal hardmask pillar.

Abstract: A bottom electrode structure for MRAM or MTJ-based memory cells comprises a taper so that the bottom CD is smaller than the top CD. A process of making a bottom electrode contact structure comprises etching a dielectric layer using a plasma chemistry with an increased degree of polymerization. We obtain a product made by this process.

Abstract: A sub-micrometer pressure sensor is provided that includes a multilayered magnetic tunnel junction (MTJ) pillar that contains a non-magnetic metallic spacer separating a first magnetic free layer from a second magnetic free layer. The presence of the non-magnetic metallic spacer in the multilayered MTJ pillar improves the sensitivity without compromising area, and makes the pressure sensor binary (either “on” or “off”) with little or no drift, and sensitivity change over time. Moreover, the resistivity switch in such a pressure sensor is instantly and a low error rate is observed.

Abstract: A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets.

Abstract: High-performance lateral bipolar junction transistors (BJTs) are provided in which a lightly doped upper intrinsic base region is formed between a lower intrinsic base region and an extrinsic base region. The lightly doped upper intrinsic base region provides two electron paths which contribute to the collector current, IC. The presence of the lightly doped upper intrinsic base region increases the total IC and leads to higher current gain, ?, if there is no increase of the base current, IB.

Abstract: A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.

Abstract: An inverter that includes an n-type field effect transistor (nFET) and a p-type field effect transistor (pFET) vertically stacked one atop the other and containing a buried metal semiconductor alloy strap that connects a drain region of the nFET to a drain region of the pFET is provided. Also, provided is a cross-coupled inverter pair with nFETs and pFETs stacked vertically.

Abstract: Structures and methods are provided for fabricating a semiconductor device (e.g., III-V compound semiconductor device) having buried resistors formed within a buffer layer of the semiconductor device. For instance, a semiconductor device includes a buffer layer disposed on a substrate, a channel layer disposed on the buffer layer, and a buried resistor disposed within the buffer layer. The buffer and channel layers may be formed of compound semiconductor materials such as III-V compound semiconductor materials. Utilizing the buffer layer of a compound semiconductor structure to form buried resistors provides a space-efficient design with increased integration density since the resistors do not have to occupy a large amount of space on the active surface of a semiconductor integrated circuit chip.

Abstract: Embodiments of the invention are directed to a method of fabricating semiconductor devices. A non-limiting example of the method includes forming a first fin in a p-type field effect transistor (PFET) region of a substrate, wherein the first fin includes a first material that includes a first type of semiconductor material at a first concentration level. A second fin is formed in an n-type FET (NFET) region of the substrate, wherein the second fin includes a second semiconductor material that includes a III-V compound. Condensation operations are performed, wherein the condensation operations are configured to increase the first concentration level in at least a portion of the first fin to a targeted final concentration level.

Abstract: A method is presented for integrating a resistive random access memory (ReRAM) device with vertical transistors on a single chip. The method includes forming a vertical field effect transistor (FET) including an epitaxial tip defining a drain terminal and forming the ReRAM device in direct contact with the epitaxial tip of the vertical FET such that a current conducting filament is formed at the epitaxial tip due to electric field enhancement.

Abstract: Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method including performing first fabrication operations to form nanosheet field effect transistor (FET) devices in a first region of a substrate. The first fabrication operations include forming a first channel nanosheet, forming a second channel nanosheet over the first channel nanosheet, forming a first gate structure around the first channel nanosheet, and forming a second gate structure around the second channel nanosheet, wherein an air gap is between the first gate structure and the second gate structure. A dopant is applied to the first gate structure and the second gate structure, wherein the dopant is configured to enter the air gap and penetrate into the first gate structure and the second gate structure from within the air gap.

Abstract: Embodiments of the invention are directed to a configuration of nanosheet FET devices formed on a substrate. A non-limiting example of the nanosheet FET devices includes a first nanosheet FET having a first channel nanosheet, a second channel nanosheet over the first nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein a first air gap is between the first gate structure and the second gate structure. The nanosheet FET devices further include a second nanosheet FET having a third channel nanosheet, a fourth channel nanosheet over the third nanosheet, a third gate structure around the third channel nanosheet, and a fourth gate structure around the fourth channel nanosheet, wherein a second air gap is between the third gate structure and the fourth gate structure.

Abstract: An integrated circuit is provided having a semiconductor structure, the semiconductor structure including a vertical field-effect transistor; and a diode wherein the vertical field-effect transistor and the diode are co-integrated in the semiconductor structure.

Abstract: A semiconductor structure and a method for fabricating the same. The structure includes a substrate and at least one semiconductor fin. The semiconductor structure further includes a channel region within the semiconductor fin. The channel region includes a higher content of germanium than remaining portions of the semiconductor fin. The semiconductor structure also includes a gate stack in contact with the semiconductor fin. The method includes removing a dummy gate formed on at least one semiconductor fin. The removal of the dummy gate exposes a channel region of the semiconductor fin. A germanium dioxide layer is formed in contact with the channel region. A condensation process is performed after the germanium dioxide layer has been formed. The condensation process increases germanium content only in the channel region.

Abstract: A replacement gate structure (i.e., functional gate structure) is formed and recessed to provide a capacitor cavity located above the recessed functional gate structure. A ferroelectric capacitor is formed in the capacitor cavity and includes a bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure. The bottom electrode structure has a topmost surface that does not extend above the U-shaped ferroelectric material liner.

Abstract: A method for forming a capacitive device comprises forming a first dielectric layer on a substrate. Portions of the first dielectric layer are removed to for form a cavity in the first dielectric layer. A first layer of conductive material is deposited on the first dielectric layer and conformally along sidewalls of the cavity. The method further includes depositing a second dielectric layer on the first layer of conductive material, and depositing a second layer of conductive material on the second dielectric layer to form a capacitive device.

Abstract: A metal-insulator-metal (MIM) capacitor is provided on a surface of an insulator layer that is located on a handle substrate. The MIM capacitor includes a first metal structure extending upwards from a first portion of the insulator layer, a second metal structure extending upwards from a second portion of the insulator layer, and an oxide fin located between the first and second metal structures, wherein the oxide fin directly contacts an entirety of a sidewall surface of the first metal structure and an entirety of a sidewall surface of the second metal structure, the oxide fin having a topmost surface that is coplanar with a topmost surface of both the first and second metal structures.

Abstract: A method of forming a stacked gate all around MOSFET is provided. A stack of alternating layers of Si and SiGe are formed on a substrate. A number of holes are etched through the stack and Si anchors formed in the holes. The SiGe layers are removed. A number of dummy gates are formed on the substrate and a Low-K spacer material deposited around the dummy gates. A number of S/D recesses are etched through the Si layers, removing the Si anchors. The dummy gates and spacer material preserves sections of the Si layers during etching, forming stacks of Si channels. S/Ds are formed in the recesses. The dummy gates are then removed replaced with metal gate stacks.