Patents by Inventor Pouya Hashemi

Pouya Hashemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NANOSCALE MAGNETIC TUNNEL JUNCTION ARRAYS FOR SUB-MICROMETER RESOLUTION PRESSURE SENSOR
    Publication number: 20200158582
    Abstract: A sub-micrometer pressure sensor including a multilayered magnetic tunnel junction (MTJ) pillar containing a magnetostrictive material layer above or below a magnetic free layer of the multilayered MTJ pillar is provided. Advanced patterning allows for scaling of the multilayered MTJ pillar down to 25 nm or below which enables the formation of a large array of extremely high resolution pressure sensors. By varying the thickness of the magnetostrictive material layer, the sensitivity of the pressure sensor can be fine tuned. Unique magnetostrictive materials in the multilayered MTJ pillar will alter the device current with the input of external pressure. Furthermore, unique arrays with much smaller critical elements can be organized in differential sensing arrangements of the multilayered MTJ pillar with pressure sensing capability that can outperform current piezoelectric based pressure sensing arrays.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 21, 2020
    Inventors: Chandrasekharan Kothandaraman, Eric Raymond Evarts, Virat Vasav Mehta, Pouya Hashemi, Alexander Reznicek
  • Formation of FinFET junction
    Patent number: 10658513
    Abstract: A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott, Alexander Reznicek
  • Vertical transistor pass gate device
    Patent number: 10658507
    Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • High-density field-enhanced ReRAM integrated with vertical transistors
    Patent number: 10658429
    Abstract: A method is presented for integrating a resistive random access memory (ReRAM) device with vertical transistors on a single chip. The method includes forming a vertical field effect transistor (FET) including an epitaxial tip defining a drain terminal and forming the ReRAM device in direct contact with the epitaxial tip of the vertical FET such that a current conducting filament is formed at the epitaxial tip due to electric field enhancement.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Alexander Reznicek
  • Vertical resistive processing unit with air gap
    Patent number: 10658582
    Abstract: A vertical resistive unit is provided. The vertical resistive unit includes first and second resistive random access memory (ReRAM) cells. The first ReRAM cell includes first vertically aligned horizontal electrode layers and first vertical electrodes operably extending through the first vertically aligned horizontal electrode layers. The second ReRAM cell includes second vertically aligned horizontal electrode layers and second vertical electrodes operably extending through the second vertically aligned horizontal electrode layers. The first and second ReRAM cells are disposed to define an air gap between the first and second ReRAM cells.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • Vertically stacked dual channel nanosheet devices
    Patent number: 10658462
    Abstract: A semiconductor structure having electrostatic control and a low threshold voltage is provided. The structure includes an nFET containing vertically stacked and suspended Si channel material nanosheets stacked vertically above a pFET containing vertically stacked and suspended SiGe channel material nanosheets. The vertically stacked nFET and pFET include a single work function metal.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Jingyun Zhang, Pouya Hashemi, Takashi Ando, Alexander Reznicek
  • Synaptic crossbar memory array
    Patent number: 10658030
    Abstract: A method of forming an Integrated Circuit (IC) chip, the IC chip and an on-chip synaptic crossbar memory array. Chip devices are formed on a surface of a semiconductor wafer. A connective layer is formed above the chip devices. A bottom electrode layer is formed on the connective layer. A neuromorphic synapse layer is formed above the bottom electrode layer with each synapse on a bottom electrode. Upper electrodes are formed above the synapses and orthogonal to bottom electrode lines. Each synapse being beneath an upper electrode where the upper electrode crosses a bottom electrode. Upper electrodes are refractory metal and the bottom electrodes are copper, or vice versa.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Talia S. Gershon, Pouya Hashemi, Bahman Hekmatshoartabari
  • DIODE CONNECTED VERTICAL TRANSISTOR
    Publication number: 20200152624
    Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • Vertical FET with Differential Top Spacer
    Publication number: 20200152769
    Abstract: VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Inventors: Takashi Ando, Choonghyun Lee, Jingyun Zhang, Pouya Hashemi
  • VERTICAL TRANSPORT FETS WITH ASYMMETRIC CHANNEL PROFILES USING DIPOLE LAYERS
    Publication number: 20200152762
    Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by forming a gradient threshold voltage adjusting gate dielectric structure between the bottom drain region of the FET and the top source region of the FET. The gradient threshold voltage adjusting gate dielectric structure includes a doped interface high-k gate dielectric material that is located in proximity to the bottom drain region and a non-doped high-k dielectric material that is located in proximity to the top source region. The non-doped high-k dielectric material has a higher threshold voltage than the doped interface high-k gate dielectric.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Inventors: Takashi Ando, Choonghyun Lee, SangHoon Shin, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek
  • STACKED NANOSHEET TECHNOLOGY WITH UNIFORM VTH CONTROL
    Publication number: 20200152737
    Abstract: A stacked nanosheet semiconductor device and method of forming are provided. In an illustrative embodiment, a gate all around (GAA) stacked nanosheet field effect transistor (FET) includes a plurality of stacked semiconductor channel nanosheet layers and a dummy nanosheet layer formed above a top one of the stacked semiconductor channel nanosheet layers, the dummy nanosheet formed from a dielectric material. The GAA stacked nanosheet FET also includes a high dielectric constant (high-k) material formed around each of the plurality of stacked semiconductor channel nanosheet layers and around the dummy nanosheet layer and a first work function (WF) metal formed around the plurality of stacked semiconductor channel nanosheet layers and the dummy nanosheet layer.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 14, 2020
    Inventors: Pouya Hashemi, Takashi Ando, Jingyun Zhang, Choonghyun Lee, Alexander Reznicek
  • TIGHTLY INTEGRATED 1T1R ReRAM FOR PLANAR TECHNOLOGY
    Publication number: 20200152866
    Abstract: A semiconductor structure includes an oxide ReRAM co-integrated with a drain region of a field effect transistor (FET). The oxide ReRAM has a tip region defined by a pointed cone that contacts a faceted upper surface of the drain region of the FET. Such a tip region enhances the electric field of the oxide ReRAM and thus helps to control forming of the conductive filament of the oxide ReRAM.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Inventors: Alexander Reznicek, Takashi Ando, Pouya Hashemi
  • REDUCTION OF METAL RESISTANCE IN VERTICAL RERAM CELLS
    Publication number: 20200152702
    Abstract: Embodiments of the invention include resulting structures and a method for fabricating a vertical ReRAM array structure. The embodiments of the invention include forming alternating layers over a metal layer of a structure, wherein a layer of the alternating layers comprises a low resistivity material, masking one or more portions of a topmost layer of the alternating layers, and etching one or more portions of the alternating layers down to the metal layer. Embodiments of the invention also include depositing a lateral electrode layer over the etched one or more portions of the alternating layers, performing an etch back on the lateral electrode layer, and forming a vertical electrode layer over the structures.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • Forming a fin using double trench epitaxy
    Patent number: 10651295
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a first trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek
  • High density antifuse co-integrated with vertical FET
    Patent number: 10651123
    Abstract: A semiconductor device comprising an anti-fuse is disclosed. The semiconductor anti-fuse includes a highly doped source of a first conductivity type overlying a substrate. The semiconductor anti-fuse further includes a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate. The semiconductor anti-fuse further includes a highly doped fuse region extending over the highly doped source and comprising an epitaxial growth, the highly doped fuse region implanted with ions.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Pouya Hashemi, Miaomiao Wang, Takashi Ando
  • SUPERHYDROPHOBIC ELECTRODE AND BIOSENSING DEVICE USING THE SAME
    Publication number: 20200141899
    Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.
    Type: Application
    Filed: January 3, 2020
    Publication date: May 7, 2020
    Inventors: Ali Afzali-Ardakani, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Decoupling capacitor on strain relaxation buffer layer
    Patent number: 10644007
    Abstract: An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Digital alloy vertical lamellae FinFET with current flow in alloy layer direction
    Patent number: 10644109
    Abstract: After forming semiconductor fins including vertically oriented alternating first digital alloy sublayer portions comprised of SiGe and second digital alloy sublayer portions comprised of Si on sidewalls of a sacrificial fin located on a substrate, the sacrificial fin is removed, leaving the semiconductor fins protruding from a top surface of the substrate. The SiGe and Si digital alloy sublayer portions are formed using isotopically enriched Si and Ge source gases to minimize isotopic mass variation in the SiGe and Si digital alloy sublayer portions.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • THREE-DIMENSIONALLY STRETCHABLE SINGLE CRYSTALLINE SEMICONDUCTOR MEMBRANE
    Publication number: 20200123677
    Abstract: A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Keith E. Fogel
  • VERTICAL TRANSISTORS HAVING A LAYER OF CHARGE CARRIERS IN THE EXTENSION REGION FOR REDUCED EXTENSION REGION RESISTANCE
    Publication number: 20200127104
    Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a fin having a fin bottom region. A charged region is formed on a sidewall of the fin bottom region, wherein the charged region includes charged particles, and wherein the fin bottom region is formed from an undoped semiconductor material. The charged particles attract charge carriers in the fin bottom region toward and adjacent to the sidewall of the fin bottom region, wherein the charge carriers form a current path through the undoped semiconductor material of the fin bottom region.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 23, 2020
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang