Patents by Inventor Pradeep Kumar

Pradeep Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160315902
    Abstract: In one embodiment, a method includes one or more computing devices accessing a notification to be sent to a user, where the notification has a context. The method also includes one or more computing devices sending a request to a history service for historical notification data associated with the user with respect to the context of the notification and a ranking of the notification where the ranking indicates a probability of the user interacting with the notification. The method also includes one or more computing devices receiving the historical notification data and the ranking from the history service. Moreover, the method also includes one or more computing devices determining a delivery policy to apply to the notification based at least in part on the context of the notification, the historical notification data, and the ranking Furthermore, the method also includes one or more computing devices applying the delivery policy to the notification to be sent to the user.
    Type: Application
    Filed: April 23, 2015
    Publication date: October 27, 2016
    Inventors: Fernando Jorge de Almeida da Silva, Martin Rehwald, Kostyantyn Fomin, Pradeep Kumar Sharma, Andrew Alexander Birchall
  • Patent number: 9480015
    Abstract: A first network device in communication with a second network device via a wireless communication link provides an indication to the second network device that the first network device will enter a power save mode. While operating in the power save mode, the first network device periodically transmits a trigger frame to the second network device to determine whether the second network device comprises buffered frames for the first network device. The first network device receives the buffered frames from the second network device responsive to transmitting the trigger frame. In another example, if both the first and the second network devices operate in the power save mode, the first network device receives a notification of available buffered frames from the second network device. The first network device transmits buffered frames destined for the second network device prior to transmitting a response to the received notification.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: October 25, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Sriman Miryala, Ashwani Kumar Dwivedi, Pradeep Kumar Yenganti
  • Patent number: 9465759
    Abstract: Systems and methods for a universal Serializer-Deserializer (SerDes) architecture are described. In various implementations, a transceiver may include: a first plurality of data flip-flops coupled to a data lookup circuit of a SerDes interface; a second plurality of data flip-flops coupled to the data lookup circuit; a plurality of latches, each latch of the plurality of latches coupled to a corresponding data flip-flop of the second plurality of data flip-flops; and a plurality of multiplexers coupled to the plurality of latches, to the first plurality of data flip-flops, and to a transmitter circuit.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: October 11, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Somasunder Kattepura Sreenath, Gururaj Kulkarni, Chandan Muddamsetty, Pradeep Kumar Ubbala
  • Patent number: 9460251
    Abstract: A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: October 4, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anand Haridass, Arun Joseph, Pradeep Kumar Nalla, Rahul M. Rao
  • Patent number: 9461584
    Abstract: A circuit includes an oscillator circuit to receive a bias current and generate an oscillating signal at an output node. A current differencing circuit subtracts a current at the output node from a reference current to generate a first current. In addition, a current mirroring circuit mirrors the first current to generate the bias current. An inverter stage is coupled to the output node, and includes an input branch configured to receive the oscillating signal and generate first and second control signals based upon the oscillating signal. At least one amplifying branch receives the first and second control signals and amplifies the first and second control signals. An output branch receives the amplified first and second control signals and generates an amplified version of the oscillating signal based upon the amplified first and second control signals.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: October 4, 2016
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Gauri Mittal, Kallol Chatterjee, Pallavi Muktesh, Nitin Jain, Pradeep Kumar Badrathwal
  • Patent number: 9447105
    Abstract: The present invention discloses triazine compounds of Formula II and a process to synthesize these compounds. Particularly, the invention provides one pot method to synthesize triazines nucleus, wherein the method comprises amination followed by using Leuckart reaction conditions of pyrrole/indole-2-carboxylates of Formula I to obtain corresponding triazine compounds of Formula II.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: September 20, 2016
    Assignee: Council of Scientific & Industrial Research
    Inventors: Pradeep Kumar, Anand Harbindu, Brijesh Sharma
  • Patent number: 9449157
    Abstract: Mechanisms to secure data on a hard reset of a device are provided. A hard reset request is detected on a handheld device. Before the hard reset is permitted to process an additional security compliance check is made. Assuming, the additional security compliance check is successful and before the hard reset is processed, the data of the handheld device is backed up to a configurable location.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: September 20, 2016
    Assignee: Novell, Inc.
    Inventors: Pradeep Kumar Chaturvedi, Prasanta Kumar Sahoo
  • Patent number: 9439863
    Abstract: This invention relates to pharmaceutical dosage forms, particularly to pH dependent pharmaceutical dosage forms with enhanced and/or prolonged distribution of a pharmaceutical compound at a target site. More specifically, this invention relates to a controlled release intravaginal pharmaceutical dosage form and, more particularly, to a pharmaceutical dosage form which comprises microspheres encapsulated and/or embedded within a bioerodible polymeric matrix, together the microspheres and the matrix are formed into a caplet and/or tablet.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: September 13, 2016
    Assignee: University of the Witwatersrand, Johannesburg
    Inventors: Viness Pillay, Yahya Essop Choonara, Felix Mashingaidse, Pradeep Kumar
  • Publication number: 20160258103
    Abstract: A tub ring mountable to an upper end of a liquid holding tub in a laundry treating appliance may include a circumferential side wall, a top wall extending radially inward from the side wall, and a plurality of radial stiffening ribs extending between the top wall and the side wall. The ribs may have a bottom edge with at least a portion inclined relative to horizontal. At least a portion of the bottom edge may also be complementary to a top wall of a balance ring.
    Type: Application
    Filed: March 5, 2015
    Publication date: September 8, 2016
    Applicant: WHIRLPOOL CORPORATION
    Inventors: JOHN M. HUNNELL, PRADEEP KUMAR, BRENNER M. SHARP, CHRISTINE L. STRAIN
  • Patent number: 9435014
    Abstract: The invention discloses the internal structures and processes to synthesize the structure of self-healing materials, especially metallic materials, metal matrix micro and nanocomposites. Self-healing is imparted by incorporation of macro, micro or nanosize hollow reinforcements including nanotubes, filled with low melting healing material or incorporation of healing material in pockets within the metallic matrix; the healing material melts and fills the crack. In another concept, macro, micro and nanosize solid reinforcements including ceramic and metallic particles, and shape memory alloys are incorporated into alloy matrices, specially nanostructured alloy matrices, to impart self healing by applying compressive stresses on the crack or diffusing material into voids to fill them.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: September 6, 2016
    Inventor: Pradeep Kumar Rohatgi
  • Patent number: 9437800
    Abstract: Systems and methods for suppressing magnetically active surface defects in superconducting quantum circuits are provided. A method includes providing one or more superconducting quantum circuits, and arranging the one or more superconducting quantum circuits in a hermetic enclosure capable of isolating the one or more superconducting circuits from ambient surroundings. The method also includes controlling an environment in the hermetic enclosure to suppress magnetically active surface defects associated with the one or more superconducting quantum circuits. In some aspects, the method further includes introducing an inert gas into the hermetic enclosure to passivate a surface of the one or more superconducting quantum circuits. In other aspects, the method further includes coating a surface of the one or more superconducting circuits with a non-magnetic encapsulation layer. In yet other aspects, the method further includes irradiating the one or more superconducting circuits using ultraviolet light.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: September 6, 2016
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Robert Francis McDermott, III, Pradeep Kumar
  • Patent number: 9436785
    Abstract: Hierarchical preset and rule base configuration of a system-on-chip (SOC) includes receiving a user input selecting a first circuit block of the SOC for enablement and determining, using a processor, a first top level preset according to the user input for the first circuit block. Selected intermediate presets are determined from a plurality of hierarchically ordered presets for the first circuit block. Low level presets are automatically determined for the first circuit block according to the selected intermediate presets for the first circuit block. The low level presets are output, e.g., by loading them into the SOC.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: September 6, 2016
    Assignee: XILINX, INC.
    Inventors: Somdutt Javre, Pradeep Kumar Mishra, Siddharth Rele
  • Publication number: 20160253446
    Abstract: A system and method for web-based interface design tool is provided. The design tool enables system designers to quickly and independently design a custom serial-link interface. The system provides interface selection and signal integrity analysis. An interface selection may interact with system designers to prompt for a set of selection criteria such as data-rate, supply rail, standard protocol, and intended application. An intelligent search engine screens through a large interface products database based on the selection criteria and provides designers with a list of devices that potentially meet the design criteria. The performance of the custom system with the selected device can be evaluated by using a web-based IBIS-AMI standard-compliant signal integrity simulator. A designers can have options to manually fine tune selected devices' parameters to iterate through different settings to determine the robustness of the solution.
    Type: Application
    Filed: February 23, 2016
    Publication date: September 1, 2016
    Applicant: Texas Instruments Incorporated
    Inventors: Kian Haur Chong, Makram Monzer Mansour, Ashwin Vishnu Kamath, Pam Srikanth, Yudhister Satija, Nithya Narayanaswamy, Khang Duy Nguyen, Pavani Jella, Jeff Perry, Pradeep Kumar Chawda
  • Publication number: 20160253439
    Abstract: A method for converting a circuit in a format of a first circuit simulation program to format of a second circuit simulation program includes identifying components in the circuit that are recognized by the second simulation program. Characteristics for components that are not recognized by the second simulation program are created. Connections in the circuit are formatted to a format that is recognized by the second simulation program. The components, characteristics, and connections are stored in a single computer-readable file.
    Type: Application
    Filed: February 25, 2016
    Publication date: September 1, 2016
    Inventors: Pradeep Kumar Chawda, Makram Mansour, Satyanandakishore Vanapalli, Ashwin Vishnu Kamath, Kian Haur Chong, Dien Mac, Jeff Perry
  • Publication number: 20160254434
    Abstract: Systems and methods for suppressing magnetically active surface defects in superconducting quantum circuits are provided. A method includes providing one or more superconducting quantum circuits, and arranging the one or more superconducting quantum circuits in a hermetic enclosure capable of isolating the one or more superconducting circuits from ambient surroundings. The method also includes controlling an environment in the hermetic enclosure to suppress magnetically active surface defects associated with the one or more superconducting quantum circuits. In some aspects, the method further includes introducing an inert gas into the hermetic enclosure to passivate a surface of the one or more superconducting quantum circuits. In other aspects, the method further includes coating a surface of the one or more superconducting circuits with a non-magnetic encapsulation layer. In yet other aspects, the method further includes irradiating the one or more superconducting circuits using ultraviolet light.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 1, 2016
    Inventors: Robert Francis McDermott III, Pradeep Kumar
  • Patent number: 9432872
    Abstract: Systems and methods are provided for allowing a multi-channel concurrent device to communicate timing information to a direct link peer, so that subsequent delivery of buffered traffic by the peer may be coordinated to minimize interference with operation of the device in another network context.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: August 30, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Sriman Miryala, Pradeep Kumar Yenganti, Ashwani Kumar Dwivedi
  • Publication number: 20160241081
    Abstract: Embodiments of the present inventive concept provide an external battery module (EBM) including a communication server board (CSB) slot configured to receive a CSB, wherein the EBM operates regardless of whether the CSB is positioned in the CSB slot; and a battery charger slot configured to receive a battery charger, wherein the EBM operates regardless of whether the battery charger is positioned in the battery charger slot.
    Type: Application
    Filed: February 12, 2015
    Publication date: August 18, 2016
    Inventors: Pradeep Kumar Nandam, David Glenn Miller
  • Publication number: 20160211698
    Abstract: A battery module is provided including a battery module connector configured to engage with a backplane connector on a backplane board associated with an uninterruptible power supply (UPS). When the battery module connector is engaged with the backplane connector a circuit is completed that instantaneously indicates to the UPS that the battery module is connected. When the battery module connector is disengaged from the backplane connector the circuit is opened and instantaneously indicates to the UPS that the battery module is disconnected.
    Type: Application
    Filed: January 21, 2015
    Publication date: July 21, 2016
    Inventors: Pradeep Kumar Nandam, David Glenn Miller
  • Publication number: 20160181978
    Abstract: A circuit includes an oscillator circuit to receive a bias current and generate an oscillating signal at an output node. A current differencing circuit subtracts a current at the output node from a reference current to generate a first current. In addition, a current mirroring circuit mirrors the first current to generate the bias current. An inverter stage is coupled to the output node, and includes an input branch configured to receive the oscillating signal and generate first and second control signals based upon the oscillating signal. At least one amplifying branch receives the first and second control signals and amplifies the first and second control signals. An output branch receives the amplified first and second control signals and generates an amplified version of the oscillating signal based upon the amplified first and second control signals.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Gauri Mittal, Kallol Chatterjee, Pallavi Muktesh, Nitin Jain, Pradeep Kumar Badrathwal
  • Patent number: 9372735
    Abstract: In various embodiments, systems and methods are presented for providing resources by way of a platform as a service in a distributed computing environment to perform a job. The system may be comprised of a number of components, such as a task machine, a task location service machine, and a high-level location service machines that in combination are useable to accomplish functions provided herein. It is contemplated that the system performs methods for providing resources by determining resources of the system, such as virtual machines, and applying auto-scaling rules to the system to scale those resources. Based on the determination of the auto-scaling rules, the resources may be allocated to achieve a desired result.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: June 21, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Bradley Gene Calder, Ju Wang, Vaman Bedekar, Sriram Sankaran, Marvin McNett, II, Pradeep Kumar Gunda, Yang Zhang, Shyam Antony, Kavitha Manivannan, Arild E Skjolsvold, Hemal Khatri