Patents by Inventor Rahul Jain

Rahul Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10700021
    Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Andrew J. Brown, Rahul Jain, Prithwish Chatterjee, Lauren A. Link, Sai Vadlamani
  • Patent number: 10700927
    Abstract: A cloud extension agent can be provided on a customer premise for interfacing, via an outbound secure connection, cloud based services. The cloud extension agent can reach the cloud based services through existing firewall infrastructure, thereby providing simple, secure deployment. Furthermore, the secure connection can enable substantially real-time communication with a cloud service to provide web-based, substantially real time control or management of resources on the customer premises via the cloud extension agent.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Vineeth Narasimhan, Joshua Lambert, Thomas Herchek, Ryan Elliot Hope, Nitish Jha, Rahul Jain, Sumeet Singh
  • Publication number: 20200204438
    Abstract: A cloud extension agent can be provided on a customer premise for interfacing, via an outbound secure connection, cloud based services. The cloud extension agent can reach the cloud based services through existing firewall infrastructure, thereby providing simple, secure deployment. Furthermore, the secure connection can enable substantially real-time communication with a cloud service to provide web-based, substantially real time control or management of resources on the customer premises via the cloud extension agent.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 25, 2020
    Inventors: Vineeth NARASIMHAN, Joshua LAMBERT, Thomas HERCHEK, Ryan Elliot HOPE, Nitish JHA, Rahul JAIN, Sumeet SINGH
  • Publication number: 20200184448
    Abstract: An example operation may include one or more of identifying, via a cognitive system, that a change in a creditworthiness attribute of a cardholder has occurred with respect to a previous creditworthiness of the cardholder, in response to identifying the change in the creditworthiness attribute of the cardholder, dynamically determining a custom interchange value for the cardholder to be used in payment transactions based on a current credit data of the cardholder, transmitting the dynamically determined custom interchange value for the cardholder to one or more blockchain peer nodes, and storing the dynamically determined custom interchange value in a hash-linked chain of blocks via a distributed ledger.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 11, 2020
    Inventor: Rahul Jain
  • Publication number: 20200176355
    Abstract: A semiconductor device package structure is provided, which includes a substrate, one or more dies coupled to the substrate, and a heat pipe device. In an example, the heat pipe device may include a conduit that is at least partially embedded within the substrate. The heat pipe device may have a first region coupled to the one or more dies. In an example, the conduit may include a first path for flow of vapor from the first region to an opposing second region. The conduit may further include a second path for flow of liquid from the second region to the first region.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 4, 2020
    Applicant: Intel Corporation
    Inventors: Robert A. May, Kristof Darmawikarta, Rahul Jain, Lilia May, Maroun Moussallem, Prithwish Chatterjee
  • Patent number: 10672859
    Abstract: An apparatus and method of forming a magnetic inductor circuit. A substrate is provided and a first magnetic layer is formed in contact with one layer of the substrate. A conductive trace is formed in contact with the first magnetic layer. A sacrificial cooper layer protects the magnetic material from wet chemistry process steps. A conductive connection is formed from the conductive trace to the outside substrate, the conductive connection comprising a horizontal connection formed by in-layer plating. A second magnetic layer is formed in contact with the conductive trace. Instead of a horizontal connection, a vertical conductive connection can be formed that is perpendicular to the magnetic layers, by drilling a first via in a second of the magnetic layers, forming a buildup layer, and drilling a second via through the buildup layer, where the buildup layer protects the magnetic layers from wet chemistry processes.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Andrew J. Brown, Rahul Jain, Sheng Li, Sai Vadlamani, Chong Zhang
  • Publication number: 20200168569
    Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.
    Type: Application
    Filed: March 30, 2017
    Publication date: May 28, 2020
    Inventors: Sai VADLAMANI, Aleksandar ALEKSOV, Rahul JAIN, Kyu Oh LEE, Kristof Kuwawi DARMAWIKARTA, Robert Alan MAY, Sri Ranga Sai BOYAPATI, Telesphor KAMGAING
  • Publication number: 20200151455
    Abstract: A system for analyzing a video file in a shortened time frame, said system comprising: a receiver (VFR) to receive a video file (VF) as an input; a Time Splitter (TR) to split the received video file according to set intervals of time depending on how fast said video is to be analyzed; a Frame splitter (FP) to split a Video Viewing Program (R) into a plurality of frames (F1, F2, . . . Fn); a Key Frame Identification mechanism (KFI) to identify key frames; and linking mechanism (LM) to cause a link to be formed with pre-populated databases and in-house libraries of images (D), of frames, which frames comprising associated tags, thereby determining a score of similar tags per video file in order to determine said genre, thereby determining multiplicity of instances for said time splitter.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Inventors: Nagender Sangra, Saurabh Singh, Rahul Jain
  • Patent number: 10643994
    Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Rahul Jain, Seo Young Kim, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani, Junnan Zhao
  • Patent number: 10623245
    Abstract: A cloud extension agent can be provided on a customer premise for interfacing, via an outbound secure connection, cloud based services. The cloud extension agent can reach the cloud based services through existing firewall infrastructure, thereby providing simple, secure deployment. Furthermore, the secure connection can enable substantially real-time communication with a cloud service to provide web-based, substantially real time control or management of resources on the customer premises via the cloud extension agent.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Vineeth Narasimhan, Joshua Lambert, Thomas Herchek, Ryan Elliot Hope, Nitish Jha, Rahul Jain, Sumeet Singh
  • Patent number: 10601705
    Abstract: Some embodiments provide a method for a first DCN operating in a first datacenter as a logical network gateway that processes messages between other DCNs of the logical network and external entities, which address the logical network gateway using a first address. The first DCN has an interface with a second address for use in the first datacenter. The method stores a mapping between the second address and a third address. A second DCN operates the logical network gateway in a second datacenter and has an interface with the third address for use in the second datacenter. From the second DCN, the method receives connection state data, describing connections between the external entities and the DCNs of the logical network, that uses the third address. The method replaces the third address with the second address in the connection state data using the stored mapping and stores the connection state data.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 24, 2020
    Assignee: NICIRA, INC.
    Inventors: Mukesh Hira, Ganesan Chandrashekhar, Jayant Jain, Rahul Jain
  • Publication number: 20200075511
    Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: Andrew J. Brown, Rahul Jain, Prithwish Chatterjee, Lauren A. Link, Sai Vadlamani
  • Publication number: 20200067734
    Abstract: Some embodiments provide a centralized overlay-network cloud gateway and a set of centralized services in a transit virtual private cloud (VPC) connected to multiple other compute VPCs hosting compute nodes (VMs, containers, etc.) that are part of (belong to) the overlay network. The centralized overlay-network cloud gateway provides connectivity between compute nodes of the overlay network (e.g., a logical network spanning multiple VPCs) and compute nodes in external networks. Some embodiments use the centralized overlay-network cloud gateway to provide transitive routing (e.g., routing through a transit VPC) in the absence of direct peering between source and destination VPCs. The overlay network, of some embodiments, uses the same subnetting and default gateway address for each compute node as the cloud provider network provided by the virtual private cloud provider.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Inventors: Mukesh Hira, Su Wang, Rahul Jain, Ganesan Chandrashekhar, Sandeep Siroya
  • Publication number: 20200067733
    Abstract: Some embodiments provide a centralized overlay-network cloud gateway and a set of centralized services in a transit virtual cloud network (VCN) connected to multiple other compute VCNs hosting compute nodes (VMs, containers, etc.) that are part of (belong to) the overlay network. The centralized overlay-network cloud gateway provides connectivity between compute nodes of the overlay network (e.g., a logical network spanning multiple VCNs) and compute nodes in external networks. Some embodiments use the centralized overlay-network cloud gateway to provide transitive routing (e.g., routing through a transit VCN) in the absence of direct peering between source and destination VCNs. The overlay network, of some embodiments, uses the same subnetting and default gateway address for each compute node as the cloud provider network provided by the virtual private cloud provider.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Inventors: Mukesh Hira, Su Wang, Rahul Jain, Ganesan Chandrashekhar, Sandeep Siroya
  • Publication number: 20200066543
    Abstract: Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.
    Type: Application
    Filed: August 27, 2018
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Rahul Jain, Sai Vadlamani, Junnan Zhao, Ji Yong Park, Kyu Oh Lee, Cheng Xu
  • Publication number: 20200066622
    Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a plurality of build-up layers. In an embodiment, the build-up layers comprise conductive traces and vias. In an embodiment, the electronics package further comprises a capacitor embedded in the plurality of build-up layers. In an embodiment, the capacitor comprises: a first electrode, a high-k dielectric layer over portions of the first electrode, and a second electrode over portions of the high-k dielectric layer.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: Rahul JAIN, Kyu Oh LEE
  • Publication number: 20200059515
    Abstract: A database proxy includes a computing device and a hardware-accelerated database proxy module. The computing device includes one or more processors, memory, a first bus interface, and a network interface coupling the database proxy to one or more networks. The database proxy module includes a second bus interface coupled to the first bus interface via one or more buses, and a request processor. The database proxy is configured to receive a database read request from a client via the one or more networks and the network interface; forward the database read request to the request processor using the one or more buses; process, using the request processor, the database read request; and return results of the database read request to the client. In some embodiments, the computing device or the database proxy module further includes a flash memory interface for accessing one or more flash memory devices.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Chidamber KULKARNI, Amarnath VISHWAKARMA, Raushan RAJ, Vijaya Raghava CHIYEDU, Rahul SACHDEV, Rahul JAIN, Prasanna SUKUMAR, Prasanna SUNDARARAJAN
  • Publication number: 20200027856
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Rahul JAIN, Ji Yong PARK, Kyu Oh LEE
  • Publication number: 20200006210
    Abstract: A chip package that includes a die coupled to a package substrate. The substrate includes a first ground layer and a dielectric material engaging the first ground layer. A solder resist layer engages the dielectric material and a routing layer is disposed at least partially within the solder resist layer. A second ground layer engages the solder resist layer.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Cheng Xu, Kyu Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park
  • Publication number: 20200007497
    Abstract: Some embodiments provide a method for a managed forwarding element (MFE) executing on a data compute node (DCN) that operates on a host computer in a public datacenter. The MFE implements a logical network that connects multiple DCNs within the public datacenter. The method receives a packet, directed to the DCN, that (i) has a first logical network source address and (ii) is encapsulated with a second source address associated with an underlying public datacenter network. The method determines whether the first logical network source address is a valid source address for the packet based on a mapping table that maps logical network addresses to underlying public datacenter network addresses. When the first source address is not a valid source address for the packet, the method drops the packet.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Rahul Jain, Mukesh Hira, Su Wang