Patents by Inventor Rahul Jain

Rahul Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200008302
    Abstract: A package substrate is disclosed. The package substrate includes a substrate core, a cavity below the substrate core that extends from a surface of a first resist layer to a bottom surface of the package substrate, and a first terminal and a second terminal in the first resist layer. The package substrate also includes one or more passive components that are coupled inside the cavity to the first terminal and the second terminal.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Rahul JAIN, Prithwish CHATTERJEE, Kyu-oh LEE
  • Publication number: 20200006005
    Abstract: Embodiments herein relate to systems, apparatuses, processing, and techniques related to patterning one or more sides of a thin film capacitor (TFC) sheet, where the TFC sheet has a first side and a second side opposite the first side. The first side and the second side of the TFC sheet are metal and are separated by a dielectric layer, and the patterned TFC sheet is to provide at least one of a capacitor or a routing feature on a first side of a substrate that has the first side and a second side opposite the first side.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Rahul JAIN, Andrew J. BROWN, Prithwish CHATTERJEE, Sai VADLAMANI, Lauren LINK
  • Publication number: 20200005994
    Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Kyu-Oh LEE, Rahul JAIN, Sai VADLAMANI, Cheng XU, Ji Yong PARK, Junnan ZHAO, Seo Young KIM
  • Publication number: 20200006464
    Abstract: An apparatus and method of forming a magnetic inductor circuit. A substrate is provided and a first magnetic layer is formed in contact with one layer of the substrate. A conductive trace is formed in contact with the first magnetic layer. A sacrificial cooper layer protects the magnetic material from wet chemistry process steps. A conductive connection is formed from the conductive trace to the outside substrate, the conductive connection comprising a horizontal connection formed by in-layer plating A second magnetic layer is formed in contact with the conductive trace. Instead of a horizontal connection, a vertical conductive connection can be formed that is perpendicular to the magnetic layers, by drilling a first via in a second of the magnetic layers, forming a buildup layer, and drilling a second via through the buildup layer, where the buildup layer protects the magnetic layers from wet chemistry processes.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Andrew J. Brown, Rahul Jain, Sheng Li, Sai Vadlamani, Chong Zhang
  • Publication number: 20190393217
    Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
    Type: Application
    Filed: May 3, 2019
    Publication date: December 26, 2019
    Inventors: Cheng Xu, Rahul Jain, Seo Young Kim, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani, Junnan Zhao
  • Publication number: 20190373736
    Abstract: Described herein are systems and methods for creating a cavity within a substrate. The systems and methods may include passing a plasma gas over a first surface of the substrate. The plasma gas may include a reactant gas. The systems and methods also may include removing a portion of the substrate by reacting the reactant gas with a constituent of the first surface of the substrate, thereby forming the cavity.
    Type: Application
    Filed: March 31, 2017
    Publication date: December 5, 2019
    Inventors: Rahul Jain, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani
  • Patent number: 10491466
    Abstract: Some embodiments provide a method and system for configuring a plurality of managed forwarding elements (MFEs) in a plurality of cloud-provider virtual networks (CPVNs) to make routing decisions that efficiently use a peered transit CPVN and peering with other CPVNs in the plurality of CPVNs. In some embodiments, a controller set receives an identification of peering relationships between CPVNs in the plurality of CPVNs and generates configuration data for configuring each MFE. The configuration data is used to configure the MFE to forward data messages received at the MFE using a peering between a source CPVN and a destination CPVN when possible and to forward data messages received at the MFE to a transit gateway device in a transit CPVN when it is not possible to use a peering between the source and destination CPVNs.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: November 26, 2019
    Assignee: VMWARE, INC.
    Inventors: Mukesh Hira, Su Wang, Rahul Jain, Ganesan Chandrashekhar, Sandeep Siroya
  • Publication number: 20190355675
    Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Inventors: Kyu-Oh LEE, Sai VADLAMANI, Rahul JAIN, Junnan ZHAO, Ji Yong PARK, Cheng XU, Seo Young KIM
  • Patent number: 10468374
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Ji Yong Park, Kyu Oh Lee
  • Publication number: 20190304933
    Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Cheng XU, Kyu-Oh LEE, Junnan ZHAO, Rahul JAIN, Ji Yong PARK, Sai VADLAMANI, Seo Young KIM
  • Publication number: 20190304661
    Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Cheng Xu, Kyu-Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park, Sai Vadlamani, Seo Young Kim
  • Publication number: 20190279806
    Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 12, 2019
    Inventors: Kristof DARMAWIKARTA, Srinivas PIETAMBARAM, Sandeep GAAN, Sri Ranga Sai BOYAPATI, Prithwish CHATTERJEE, Sameer PAITAL, Rahul JAIN, Junnan ZHAO
  • Publication number: 20190250326
    Abstract: This document discusses, among other things, a waveguide including a first metal having an outer surface proximate a dielectric material and an inner surface defining a path of the waveguide, a method of receiving an optical signal at the inner surface of the waveguide and transmitting the optical signal along at least a portion of the path of the waveguide. A method of integrating a waveguide in a substrate includes depositing sacrificial metal on a first surface of a carrier substrate to form a core of the waveguide, depositing a first metal over the sacrificial metal and at least a portion of the first surface of the carrier substrate, forming an outer surface of the waveguide and a conductor separate from the sacrificial metal, and depositing dielectric material over the first surface of the carrier substrate about the conductor.
    Type: Application
    Filed: December 14, 2015
    Publication date: August 15, 2019
    Inventors: Robert Alan May, Kristof Darmawikarta, Rahul Jain, Sri Ranga Sai Boyapati, Maroun Moussallem, Rahul N. Manepalli, Srinivas Pietambaram
  • Patent number: 10379996
    Abstract: A device may receive information associated with a software program executing on a device, and may generate event records based on the information associated with the software program. The device may identify pattern information associated with the event records, and may perform data analytics on the event records and the pattern information to identify one or more defects associated with the software program and to determine an expected behavior of the software program. The device may generate one or more reports based on the one or more defects associated with the software program and the expected behavior of the software program, and may provide the one or more reports.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: August 13, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Vijayendra Kumar Gupta, Mallikarjun Tallapragada, Rahul Jain
  • Publication number: 20190244922
    Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Rahul JAIN, Kyu Oh LEE, Amanda E. SCHUCKMAN, Steve S. CHO
  • Patent number: 10373951
    Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Rahul Jain, Seo Young Kim, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani, Junnan Zhao
  • Publication number: 20190221345
    Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Applicant: Intel Corporation
    Inventors: Sai Vadlamani, Prithwish Chatterjee, Rahul Jain, Kyu Oh Lee, Sheng C. Li, Andrew J. Brown, Lauren A. Link
  • Publication number: 20190206780
    Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Prithwish Chatterjee, Junnan Zhao, Sai Vadlamani, Ying Wang, Rahul Jain, Andrew J. Brown, Lauren A. Link, Cheng Xu, Sheng C. Li
  • Patent number: 10324821
    Abstract: A system and method for facilitating characterizing customized computing objects of a software application, such as a networked enterprise application. An example method includes identifying one or more custom computing objects of one or more software applications of a computing environment; determining one or more grouping criteria for grouping identified custom objects; grouping information pertaining to the one or more custom objects based on the one or more grouping criteria, resulting in one or more custom object groupings; and using the one or more custom object groupings, with reference to data characterizing one or more changes slated to be made to the software application, to generate one or more user interface display screens. In a more specific embodiment, the data characterizing one or more changes includes metadata characterizing core software application maintenance events, upgrades, and/or other modifications.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: June 18, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Shamus Kahl, Nathan Rooney, Stephen J. Wilson, Rahul Jain, Saumyaranjan Acharya, Stephen Persky, Ankit Kapil
  • Publication number: 20190173780
    Abstract: Some embodiments provide a method for a first DCN operating in a first datacenter as a logical network gateway that processes messages between other DCNs of the logical network and external entities, which address the logical network gateway using a first address. The first DCN has an interface with a second address for use in the first datacenter. The method stores a mapping between the second address and a third address. A second DCN operates the logical network gateway in a second datacenter and has an interface with the third address for use in the second datacenter. From the second DCN, the method receives connection state data, describing connections between the external entities and the DCNs of the logical network, that uses the third address. The method replaces the third address with the second address in the connection state data using the stored mapping and stores the connection state data.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 6, 2019
    Inventors: Mukesh Hira, Ganesan Chandrashekhar, Jayant Jain, Rahul Jain