Abstract: A wireless data communication system has a first station or mobile unit is linked to a second station configured as an access unit to support packet communication, voice or data, where the voice packets are transmitted in the Continuously Aware Mode (CAM) mode while other packets are buffered by the access point and held until asked for by the first station when in a Power Saving-Poll (PSP) mode. A monitoring apparatus at the access point monitors all transmitted packets and sorts the packets to the mobile unit according to CAM or PSP mode. Voice packets are sent out immediately to the mobile unit. Other packets are stored at the access point. The packet arrival rate may vary during transmission and due to random packet delays introduced by propagation characteristic and processing apparatus. The packet arrival rate and delays are taken into account by the first station in an algorithm to determine and extend the normal safe period in which the station receiver may be powered off.

Abstract: A power semiconductor device that includes common conduction regions, charge compensation regions, each adjacent a respective common conduction region, and a stand off region over the common conduction regions and charge compensation regions.

Abstract: III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure may include a dielectric layer that is epitaxially grown using a III-nitride material to provide a simplified manufacturing process. The process permits the use of planar manufacturing technology to avoid additional manufacturing costs. High voltage power ICs have improved performance in a smaller package in comparison to corresponding silicon structures.

Abstract: A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation and containing an oxygen surfactant layer to form a more uniform MgO layer and lower breakdown distribution percent. A CoFeB/NCC/CoFeB composite free layer with a middle nanocurrent channel layer minimizes Jc0 while enabling thermal stability, write voltage, read voltage, and Hc values that satisfy 64 Mb design requirements. The NCC layer has RM grains in an insulator matrix where R is Co, Fe, or Ni, and M is a metal such as Si or Al. NCC thickness is maintained around the minimum RM grain size to avoid RM granules not having sufficient diameter to bridge the distance between upper and lower CoFeB layers. A second NCC layer and third CoFeB layer may be included in the free layer or a second NCC layer may be inserted below the Ru capping layer.

Abstract: A III-nitride heterojunction semiconductor device that includes a power electrode that is electrically connected to a conductive substrate through a trench in the heterojunction thereof.

Abstract: An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer.

Abstract: A semi-conductor crystal and method of forming the same. The method includes providing a flow of dopant and column III element containing gases, then stopping flow of dopant and column III element containing gases, reducing the temperature, restarting flow of column III containing gases and then elevating the temperature.

Abstract: An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 ? to 900 ?. In a preferred embodiment, the thickness is 600 ?.

Abstract: A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer.

Abstract: An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.

Abstract: A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.

Abstract: A III-nitride power semiconductor device that includes a nitrogen polar active heterojunction having a two-dimensional electron gas and including a first III-nitride semiconductor body by one band gap and a second III-nitride body having another band gap over the first III-nitride semiconductor body, a gate arrangement, a gate barrier under the gate arrangement thereof, a first power electrode and a second power electrode, and a method for fabricating the device.

Abstract: An N-polar III-nitride heterojunction JFET which includes a P-type III-nitride body under the gate electrode thereof.

Abstract: A wireless data communications system includes simplified access points which are connected to ports of an intelligent switching hub. The switching hub relays data packets to the access points in accordance with destination address data in the data communications. In a preferred arrangement the access points are provided with power over the data cable from the switching hub location.

Abstract: An improved portable shopping system with improved data presentation system for presenting customer desired data on a portable terminal. The portable terminal includes audio as well as video presentation components that are used to provide customer specific marketing files to promote the sale of identified items.

Abstract: A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by a NOX process, a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel layer to minimize Jc0, and a Ru capping layer to enhance the spin scattering effect and increase dR/R. Good write margin is achieved by modifying the NOX process to afford a RA less than 10 ohm-?m2 and good read margin is realized with a dR/R of >100% by annealing at 330° C. or higher to form crystalline CoFeB free layers. The NCC thickness is maintained in the 6 to 10 Angstrom range to reduce Rp and avoid Fe(Si) granules from not having sufficient diameter to bridge the distance between upper and lower CoFeB layers. A FeSiO layer may be inserted below the Ru layer in the capping layer to prevent the Ru from causing a high damping constant in the upper CoFeB free layer.

Abstract: A III-nitride based field effect transistor obtains improved performance characteristics through manipulation of the relationship between the in-plane lattice constant of the interface of material layers. A high mobility two dimensional electron gas generated at the interface of the III-nitride materials permits high current conduction with low ON resistance, and is controllable through the manipulation of spontaneous polarization fields obtained according to the characteristics of the III-nitride material. The field effect transistor produced can be made to be a nominally on device where the in-plane lattice constants of the material forming the interface match. A nominally off device may be produced where one of the material layers has an in-plane lattice constant that is larger than that of the other layer material. The layer materials are preferably InAlGaN/GaN layers that are particularly tailored to the characteristics of the present invention.

Abstract: A wireless data communications system includes simplified access points which are connected to ports of an intelligent switching hub. The switching hub relays data packets to the access points in accordance with destination address data in the data communications. In a preferred arrangement the access points are provided with power over the data cable from the switching hub location.

Abstract: An embodiment of a III-nitride semiconductor device and method for making the same may include a low resistive passivation layer that permits the formation of device contacts without damage to the III-nitride material during high temperature processing. The passivation layer may be used to passivate the entire device. The passivation layer may also be provided in between contacts and active layers of the device to provide a low resistive path for current conduction. The passivation process may be used with any type of device, including FETs, rectifiers, schottky diodes and so forth, to improve breakdown voltage and prevent field crowding effects near contact junctions. The passivation layer may be activated with a low temperature anneal that does not impact the III-nitride device regarding outdiffusion.

Abstract: A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and a gate electrode that does not overlap the top surface of the field dielectric bodies and is disposed over a well in the III-nitride heterojunction.