Patents by Inventor Sameer Pendharkar

Sameer Pendharkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TRENCH GATE TRENCH FIELD PLATE VERTICAL MOSFET
    Publication number: 20170373184
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
    Type: Application
    Filed: June 30, 2017
    Publication date: December 28, 2017
    Inventors: Marie Denison, Sameer Pendharkar, Guru Mathur
  • High voltage lateral DMOS transistor with optimized source-side blocking capability
    Patent number: 9831320
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: November 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Bi-directional ESD protection circuit
    Patent number: 9812439
    Abstract: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: November 7, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy Patrick Pauletti, Sameer Pendharkar, Wayne Tien-Feng Chen, Jonathan Brodsky, Robert Steinhoff
  • High voltage drain extension on thin buried oxide SOI
    Patent number: 9806190
    Abstract: An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: October 31, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Philip L. Hower, Sameer Pendharkar
  • HIGH VOLTAGE CMOS WITH TRIPLE GATE OXIDE
    Publication number: 20170301673
    Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Inventors: Binghua Hu, Pinghai Hao, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Jacobs
  • High voltage lateral DMOS transistor with optimized source-side blocking capability
    Patent number: 9793375
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 17, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Dual deep trenches for high voltage isolation
    Patent number: 9786665
    Abstract: A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 10, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Binghua Hu, Alexei Sadovnikov, Guru Mathur
  • ISOLATED III-N SEMICONDUCTOR DEVICES
    Publication number: 20170250272
    Abstract: A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.
    Type: Application
    Filed: May 17, 2017
    Publication date: August 31, 2017
    Inventors: Naveen Tipirneni, Sameer Pendharkar
  • High voltage CMOS with triple gate oxide
    Patent number: 9741718
    Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: August 22, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Pinghai Hao, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Jacobs
  • Reduced area power devices using deep trench isolation
    Patent number: 9735265
    Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 15, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yongxi Zhang, Sameer Pendharkar, Seetharaman Sridhar
  • TRENCH GATE TRENCH FIELD PLATE VERTICAL MOSFET
    Publication number: 20170222040
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
    Type: Application
    Filed: April 12, 2017
    Publication date: August 3, 2017
    Inventors: Marie DENISON, Sameer PENDHARKAR, Guru MATHUR
  • Isolated III-N semiconductor devices
    Patent number: 9685545
    Abstract: A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: June 20, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Naveen Tipirneni, Sameer Pendharkar
  • ISOLATED III-N SEMICONDUCTOR DEVICES
    Publication number: 20170148905
    Abstract: A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.
    Type: Application
    Filed: November 25, 2015
    Publication date: May 25, 2017
    Inventors: Naveen Tipirneni, Sameer Pendharkar
  • Trench gate trench field plate vertical MOSFET
    Patent number: 9660021
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: May 23, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Sameer Pendharkar, Guru Mathur
  • DEEP TRENCH ISOLATION WITH TANK CONTACT GROUNDING
    Publication number: 20170133261
    Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.
    Type: Application
    Filed: January 23, 2017
    Publication date: May 11, 2017
    Inventors: Yongxi Zhang, Eugen Mindricelu, Sameer Pendharkar, Seetharaman Sridhar
  • TRENCH GATE TRENCH FIELD PLATE VERTICAL MOSFET
    Publication number: 20170125513
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
    Type: Application
    Filed: January 11, 2017
    Publication date: May 4, 2017
    Inventors: Marie DENISON, Sameer PENDHARKAR, Guru MATHUR
  • AVALANCHE ENERGY HANDLING CAPABLE III-NITRIDE TRANSISTORS
    Publication number: 20170098702
    Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI
  • Semiconductor structure with a doped region between two deep trench isolation structures
    Patent number: 9608105
    Abstract: The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: March 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Takehito Tamura, Binghua Hu, Sameer Pendharkar, Guru Mathur
  • HIGH VOLTAGE LATERAL EXTENDED DRAIN MOS TRANSISTOR WITH IMPROVED DRIFT LAYER CONTACT
    Publication number: 20170084737
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Philip Leland HOWER, Sameer PENDHARKAR, Marie DENISON
  • REDUCED AREA POWER DEVICES USING DEEP TRENCH ISOLATION
    Publication number: 20170062611
    Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.
    Type: Application
    Filed: November 10, 2016
    Publication date: March 2, 2017
    Inventors: Yongxi ZHANG, Sameer PENDHARKAR, Seetharaman SRIDHAR