Patents by Inventor Sameer Pendharkar

Sameer Pendharkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Drain extended CMOS with counter-doped drain extension
    Patent number: 9583596
    Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: February 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philipp Steinmann, Amitava Chatterjee, Sameer Pendharkar
  • Trench gate trench field plate vertical MOSFET
    Patent number: 9577033
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: February 21, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Sameer Pendharkar, Guru Mathur
  • Method of forming a semiconductor device having a GaNFET, an overvoltage clamping component, and a voltage dropping component
    Patent number: 9559093
    Abstract: A method of forming a semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component has a breakdown voltage less than a breakdown voltage of the GaN FET. The voltage dropping component is formed to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: January 31, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • III-nitride device and method having a gate isolating structure
    Patent number: 9553151
    Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: January 24, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni, Jungwoo Joh
  • Deep trench isolation with tank contact grounding
    Patent number: 9553011
    Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: January 24, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yongxi Zhang, Eugen Mindricelu, Sameer Pendharkar, Seetharaman Sridhar
  • Driver for normally on III-nitride transistors to get normally-off functionality
    Patent number: 9543944
    Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: January 10, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • High voltage lateral extended drain MOS transistor with improved drift layer contact
    Patent number: 9543149
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: January 10, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Reduced area power devices using deep trench isolation
    Patent number: 9525060
    Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: December 20, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yongxi Zhang, Sameer Pendharkar, Seetharaman Sridhar
  • High voltage depletion mode N-channel JFET
    Patent number: 9508869
    Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • LOW-COST CMOS STRUCTURE WITH DUAL GATE DIELECTRICS AND METHOD OF FORMING THE CMOS STRUCTURE
    Publication number: 20160322263
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Apparatus and methods for qualifying HEMT FET devices
    Patent number: 9476933
    Abstract: A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: October 25, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jungwoo Joh, Srikanth Krishnan, Sameer Pendharkar
  • LATERAL MOSFET WITH BURIED DRAIN EXTENSION LAYER
    Publication number: 20160300946
    Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 13, 2016
    Inventors: Marie DENISON, Philip L. HOWER, Sameer PENDHARKAR
  • INTEGRATION OF HEAT SPREADER FOR BEOL THERMAL MANAGEMENT
    Publication number: 20160300775
    Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.
    Type: Application
    Filed: June 16, 2016
    Publication date: October 13, 2016
    Inventors: Archana Venugopal, Marie Denison, Luigi Colombo, Sameer Pendharkar
  • FAST SWITCHING IGBT WITH EMBEDDED EMITTER SHORTING CONTACTS AND METHOD FOR MAKING SAME
    Publication number: 20160276459
    Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or grown epitaxial silicon for controlled drift region thickness and fast switching speed.
    Type: Application
    Filed: May 31, 2016
    Publication date: September 22, 2016
    Inventors: Jacek Korec, John Manning Savidge Neilson, Sameer Pendharkar
  • DRIVER FOR NORMALLY ON III-NITRIDE TRANSISTORS TO GET NORMALLY-OFF FUNCTIONALITY
    Publication number: 20160277021
    Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.
    Type: Application
    Filed: May 31, 2016
    Publication date: September 22, 2016
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI
  • Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
    Patent number: 9431302
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 30, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • AVALANCHE ENERGY HANDLING CAPABLE III-NITRIDE TRANSISTORS
    Publication number: 20160247795
    Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 25, 2016
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI
  • Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
    Patent number: 9412668
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 9, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Lateral MOSFET with buried drain extension layer
    Patent number: 9397211
    Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Philip L. Hower, Sameer Pendharkar
  • Layer transfer of silicon onto III-nitride material for heterogenous integration
    Patent number: 9396948
    Abstract: An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Naveen Tipirneni, Sameer Pendharkar, Rick L. Wise