Patents by Inventor Sameer Pendharkar

Sameer Pendharkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HIGH VOLTAGE CMOS WITH TRIPLE GATE OXIDE
    Publication number: 20150325577
    Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
    Type: Application
    Filed: July 20, 2015
    Publication date: November 12, 2015
    Inventors: Binghua Hu, Pinghai Hao, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Jacobs
  • Low cost transistors
    Patent number: 9184163
    Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: November 10, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar
  • Controlled on and off time scheme for monolithic cascoded power transistors
    Patent number: 9159725
    Abstract: A semiconductor device includes a depletion mode GaN FET cascoded with an enhancement mode NMOS transistor. A gate of the GaN FET is electrically coupled to a source of the NMOS transistor through a gate network. The gate network controls at least one of a turn-on time and a turn-off time of the GaN FET. The gate network may be controlled by an input signal to a gate of the NMOS transistor.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: October 13, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hassan P. Forghani-Zadeh, Sameer Pendharkar
  • DRIVER FOR NORMALLY ON III-NITRIDE TRANSISTORS TO GET NORMALLY-OFF FUNCTIONALITY
    Publication number: 20150287641
    Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI
  • SEMICONDUCTOR STRUCTURE WITH A DOPED REGION BETWEEN TWO DEEP TRENCH ISOLATION STRUCTURES
    Publication number: 20150270391
    Abstract: The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers.
    Type: Application
    Filed: June 4, 2015
    Publication date: September 24, 2015
    Inventors: Takehito Tamura, Binghua Hu, Sameer Pendharkar, Guru Mathur
  • III-NITRIDE DEVICE AND METHOD HAVING A GATE ISOLATING STRUCTURE
    Publication number: 20150270357
    Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.
    Type: Application
    Filed: June 5, 2015
    Publication date: September 24, 2015
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI, Jungwoo JOH
  • Trench gate trench field plate semi-vertical semi-lateral MOSFET
    Patent number: 9136368
    Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: September 15, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Sameer Pendharkar, Guru Mathur
  • LOW-COST CMOS STRUCTURE WITH DUAL GATE DIELECTRICS AND METHOD OF FORMING THE CMOS STRUCTURE
    Publication number: 20150249040
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 3, 2015
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • LOW-COST CMOS STRUCTURE WITH DUAL GATE DIELECTRICS AND METHOD OF FORMING THE CMOS STRUCTURE
    Publication number: 20150249088
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 3, 2015
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Vertical trench MOSFET device in integrated power technologies
    Patent number: 9123802
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: September 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Guru Mathur, Marie Denison, Sameer Pendharkar
  • METHOD TO FORM STEPPED DIELECTRIC FOR FIELD PLATE FORMATION
    Publication number: 20150243742
    Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.
    Type: Application
    Filed: May 7, 2015
    Publication date: August 27, 2015
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI
  • MECHANICALLY ROBUST SILICON SUBSTRATE HAVING GROUP IIIA-N EPITAXIAL LAYER THEREON
    Publication number: 20150243494
    Abstract: A method of forming an epitaxial article includes growing a crystal of elemental silicon having a minimum boron doping level of 3.2×1018/cm3 using Czochralski process parameters including a crystal growth velocity (pull speed) [V] which is less than (<) an average axial temperature gradient [G]. The crystal is cut into at least one elemental silicon substrate having a surface aligned to a <111> direction; wherein a ratio of vacancies/interstitials in the silicon substrate is less than (<) 1. At least one epitaxial buffer layer is grown on the surface of the silicon substrate, and at least one epitaxial Group IIIA-N layer is grown on the buffer layer(s).
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: MICHAEL LOUIS HAYDEN, THOMAS ANTHONY MCKENNA, RICK L. WISE, SAMEER PENDHARKAR
  • Low cost transistors
    Patent number: 9117691
    Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar
  • High voltage CMOS with triple gate oxide
    Patent number: 9117687
    Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Pinghai Hao, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Jacobs
  • AVALANCHE ENERGY HANDLING CAPABLE III-NITRIDE TRANSISTORS
    Publication number: 20150221747
    Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.
    Type: Application
    Filed: April 16, 2015
    Publication date: August 6, 2015
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI
  • SINKER WITH A REDUCED WIDTH
    Publication number: 20150214096
    Abstract: The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.
    Type: Application
    Filed: April 9, 2015
    Publication date: July 30, 2015
    Inventors: Binghua HU, Sameer PENDHARKAR, Guru MATHUR, Takehito TAMURA
  • Driver for normally on III-nitride transistors to get normally-off functionality
    Patent number: 9093301
    Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 28, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • JFET having width defined by trench isolation
    Patent number: 9076760
    Abstract: A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: July 7, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Pinghai Hao, Sameer Pendharkar
  • Semiconductor structure with a doped region between two deep trench isolation structures
    Patent number: 9076863
    Abstract: The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: July 7, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Takehito Tamura, Binghua Hu, Sameer Pendharkar, Guru Mathur
  • HIGH VOLTAGE DEPLETION MODE N-CHANNEL JFET
    Publication number: 20150179452
    Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 25, 2015
    Inventors: Philip Leland HOWER, Sameer PENDHARKAR, Marie DENISON