Patents by Inventor Sameer Pendharkar

Sameer Pendharkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LATERAL MOSFET WITH BURIED DRAIN EXTENSION LAYER
    Publication number: 20150179793
    Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.
    Type: Application
    Filed: December 3, 2014
    Publication date: June 25, 2015
    Inventors: Marie DENISON, Philip L. HOWER, Sameer PENDHARKAR
  • Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
    Patent number: 9064726
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: June 23, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • REDUCED AREA POWER DEVICES USING DEEP TRENCH ISOLATION
    Publication number: 20150171211
    Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.
    Type: Application
    Filed: December 8, 2014
    Publication date: June 18, 2015
    Inventors: Yongxi ZHANG, Sameer PENDHARKAR, Seetharaman SRIDHAR
  • HIGH VOLTAGE LATERAL DMOS TRANSISTOR WITH OPTIMIZED SOURCE-SIDE BLOCKING CAPABILITY
    Publication number: 20150171212
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 18, 2015
    Inventors: Philip Leland HOWER, Sameer PENDHARKAR, Marie DENISON
  • HIGH VOLTAGE LATERAL EXTENDED DRAIN MOS TRANSISTOR WITH IMPROVED DRIFT LAYER CONTACT
    Publication number: 20150171213
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 18, 2015
    Inventors: Philip Leland HOWER, Sameer PENDHARKAR, Marie DENISON
  • Apparatus and Methods for Qualifying HEMT FET Devices
    Publication number: 20150160285
    Abstract: A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.
    Type: Application
    Filed: November 19, 2014
    Publication date: June 11, 2015
    Inventors: Jungwoo Joh, Srikanth Krishnan, Sameer Pendharkar
  • Method to form stepped dielectric for field plate formation
    Patent number: 9054071
    Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: June 9, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • III-nitride device and method having a gate isolating structure
    Patent number: 9054027
    Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: June 9, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni, Jungwoo Joh
  • Avalanche energy handling capable III-nitride transistors
    Patent number: 9035318
    Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: May 19, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • BI-DIRECTIONAL ESD PROTECTION CIRCUIT
    Publication number: 20150103451
    Abstract: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 16, 2015
    Inventors: Timothy Patrick Pauletti, Sameer Pendharkar, Wayne Tien-Feng Chen, Jonathan Brodsky, Robert Steinhoff
  • TRENCH GATE TRENCH FIELD PLATE SEMI-VERTICAL SEMI-LATERAL MOSFET
    Publication number: 20150097225
    Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Marie DENISON, Sameer PENDHARKAR, Guru MATHUR
  • VERTICAL TRENCH MOSFET DEVICE IN INTEGRATED POWER TECHNOLOGIES
    Publication number: 20150097231
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Guru MATHUR, Marie DENISON, Sameer PENDHARKAR
  • TRENCH GATE TRENCH FIELD PLATE VERTICAL MOSFET
    Publication number: 20150097230
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Marie DENISON, Sameer PENDHARKAR, Guru MATHUR
  • SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE WITH DEEP TRENCH ISOLATION STRUCTURES
    Publication number: 20150021687
    Abstract: The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Takehito Tamura, Binghua Hu, Sameer Pendharkar, Guru Mathur
  • CONTROLLED ON AND OFF TIME SCHEME FOR MONOLITHIC CASCODED POWER TRANSISTORS
    Publication number: 20150021614
    Abstract: A semiconductor device includes a depletion mode GaN FET cascoded with an enhancement mode NMOS transistor. A gate of the GaN FET is electrically coupled to a source of the NMOS transistor through a gate network. The gate network controls at least one of a turn-on time and a turn-off time of the GaN FET. The gate network may be controlled by an input signal to a gate of the NMOS transistor.
    Type: Application
    Filed: July 19, 2013
    Publication date: January 22, 2015
    Inventors: Hassan P. Forghani-Zadeh, Sameer Pendharkar
  • III-nitride enhancement mode transistors with tunable and high gate-source voltage rating
    Patent number: 8933461
    Abstract: A semiconductor device includes an enhancement mode GaN FET with a depletion mode GaN FET electrically coupled in series between a gate node of the enhancement mode GaN FET and a gate terminal of the semiconductor device. A gate node of the depletion mode GaN FET is electrically coupled to a source node of the enhancement mode GaN FET. A source node of said enhancement mode GaN FET is electrically coupled to a source terminal of the semiconductor device, a drain node of the enhancement mode GaN FET is electrically coupled to a drain terminal of said semiconductor device, and a drain node of the depletion mode GaN FET is electrically coupled to a gate terminal of the semiconductor device.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: January 13, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • BI-DIRECTIONAL GALLIUM NITRIDE SWITCH WITH SELF-MANAGED SUBSTRATE BIAS
    Publication number: 20140374766
    Abstract: A semiconductor device includes a bidirectional GaN FET formed on a non-insulating substrate. The semiconductor device further includes a first electrical clamp connected between the substrate and a first source/drain node of the bidirectional GaN FET, and a second electrical clamp connected between the substrate and a second source/drain node of the bidirectional GaN FET. The first clamp and the second clamp are configured to bias the substrate at a lower voltage level of an applied bias to the first source/drain node and an applied bias to the second source/drain node, within an offset voltage of the relevant clamp.
    Type: Application
    Filed: June 20, 2013
    Publication date: December 25, 2014
    Inventors: Sandeep R. BAHL, Matthew SENESKY, Naveen TIPIRNENI, David I. ANDERSON, Sameer PENDHARKAR
  • METHOD TO FORM STEPPED DIELECTRIC FOR FIELD PLATE FORMATION
    Publication number: 20140339671
    Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 20, 2014
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI
  • Bi-directional ESD protection circuit
    Patent number: 8890248
    Abstract: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: November 18, 2014
    Assignee: Texas Instruments Incorporation
    Inventors: Timothy Patrick Pauletti, Sameer Pendharkar, Wayne Tien-Feng Chen, Jonathan Brodsky, Robert Steinhoff
  • AVALANCHE ENERGY HANDLING CAPABLE III-NITRIDE TRANSISTORS
    Publication number: 20140327010
    Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 6, 2014
    Applicant: Texas Instuments Incorporated
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI