Patents by Inventor Sang-Don Lee

Sang-Don Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTERNAL VOLTAGE GENERATION CIRCUIT
    Publication number: 20120274380
    Abstract: An internal voltage generation circuit includes a first detection unit, a second detection unit, a control unit, and a voltage pumping unit. The first detection unit compares an internal voltage with a first reference voltage to generate a first detection signal when the first detection unit is activated in response to a first enable signal. The second detection unit compares the internal voltage with a second reference voltage to generate a second detection signal. The control unit generates the first enable signal and a second enable signal in response to the first detection signal and the second detection signal. The voltage pumping unit generates the internal voltage in response to the second enable signal.
    Type: Application
    Filed: July 21, 2011
    Publication date: November 1, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Sang Don LEE
  • Aerosol particle deposition on surfaces
    Patent number: 8286517
    Abstract: A method and apparatus for generating a standardized surface contaminated by an aerosol deposited on its surface is described. Aerosols are propelled horizontally onto a vertical surface. The standardized contaminated surface is used to evaluate the effectiveness of cleaning and removing techniques.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: October 16, 2012
    Assignee: The United States of America as represented by the Administrator of the U.S. Environments Protection Agency
    Inventors: Sang Don Lee, Shawn P. Ryan, Emily G. Snyder
  • Method of manufacuturing semiconductor memory apparatus and semiconductor memory apparatus manufactured thereby
    Patent number: 8198167
    Abstract: A method of manufacturing a semiconductor memory apparatus includes fabricating a cell array to reduce parasite capacitance generated between a bit line and a gate pattern. The method may include determining a plug region by a storage-node plug contact mask and a bit line plug mask. The method may further include: forming a gate pattern of a cell transistor and depositing an insulation layer over a structure including the gate pattern; and forming a hard mask layer over the insulation layer.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: June 12, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Don Lee
  • Method for fabricating semiconductor device
    Patent number: 8187940
    Abstract: A method for fabricating a semiconductor device, including (a) etching a semiconductor substrate to form a first trench defining an active region; (b) forming a first spacer on sidewalls of the first trench; (c) etching a bottom of the first trench to form a second trench; (d) etching a sidewall of the second trench to form a third trench including an undercut space; (e) forming a device isolation structure that fills the first, second and third trenches; (f) etching the semiconductor substrate of a gate region to form a recess; and (g) forming a gate that fills the recess.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang Don Lee, Jae Goan Jeong
  • SEMICONDUCTOR DEVICE WITH RECESS AND FIN STRUCTURE
    Publication number: 20120122295
    Abstract: The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess.
    Type: Application
    Filed: January 27, 2012
    Publication date: May 17, 2012
    Applicant: 658868 N.B. INC.
    Inventors: Sang Don LEE, Sung Woong Chung
  • VERTICAL LIGHT-EMITTING DEVICE
    Publication number: 20120091434
    Abstract: A vertical light-emitting device includes: a substrate; a first electrode disposed on a bottom surface of the substrate; a reflection layer disposed on a top surface of the substrate; a current spreading layer disposed on the reflection layer and comprising a groove having a width narrower toward a top portion thereof; a light generation layer disposed on the current spreading layer; and a second electrode disposed on the light generation layer.
    Type: Application
    Filed: August 31, 2011
    Publication date: April 19, 2012
    Inventors: Hyun-kwon HONG, Sang-don Lee, Kwang-min Song, Kee-won Lee
  • Semiconductor Device
    Publication number: 20120074473
    Abstract: A method for fabricating a semiconductor device comprises forming a partial-insulated substrate comprising an insulating region located below both a channel region of a cell transistor and one of a storage node contact region and a bit line contact region, and forming a cell transistor comprising a fin region on the partial-insulated substrate.
    Type: Application
    Filed: December 7, 2011
    Publication date: March 29, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Sang Don Lee
  • Semiconductor memory device for low voltage
    Patent number: 8125844
    Abstract: A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device efficiently operates with low voltage without any degradation of operation speed.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: February 28, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hee-Bok Kang, Jin-Hong Ahn, Sang-Don Lee
  • Transistor of volatile memory device with gate dielectric structure capable of trapping charges
    Patent number: 8115244
    Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: February 14, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Don Lee, Yil-Wook Kim, Jin-Hong Ahn, Young-June Park
  • Semiconductor device with recess and fin structure
    Patent number: 8110871
    Abstract: The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: February 7, 2012
    Assignee: 658868 N.B. Inc.
    Inventors: Sang Don Lee, Sung Woong Chung
  • Semiconductor device including partial silicon on insulator fin structure and method for fabricating the same
    Patent number: 8093111
    Abstract: A method for fabricating a semiconductor device comprises forming a partial-insulated substrate comprising an insulating region located below both a channel region of a cell transistor and one of a storage node contact region and a bit line contact region, and forming a cell transistor comprising a fin region on the partial-insulated substrate.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: January 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Don Lee
  • Semiconductor memory apparatus
    Patent number: 8085572
    Abstract: A semiconductor memory apparatus includes a unit cell with a transistor having a floated body and a capacitor for storing charges; a word line for activating the unit cell; and a bit line for transmitting data to the unit cell.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: December 27, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang Don Lee, Jung Ho Lee, Tae Su Jang
  • Method of Fabricating a Transistor
    Publication number: 20110287599
    Abstract: A method of fabricating a saddle-fin transistor may include: forming a buffer oxide film and a hard mask oxide film over a semiconductor substrate; etching the buffer oxide film, the hard mask oxide film and the semiconductor substrate corresponding to a mask pattern to form a trench corresponding to a gate electrode and a fin region; oxidizing the exposed semiconductor substrate in the trench to form a gate oxide film; depositing a gate lower electrode in the trench; and depositing a gate upper electrode over the gate lower electrode to fill the trench.
    Type: Application
    Filed: August 2, 2011
    Publication date: November 24, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Sang Don Lee
  • Method for manufacturing semiconductor apparatus having saddle-fin transistor and semiconductor apparatus fabricated thereby
    Patent number: 8026138
    Abstract: A method for manufacturing a semiconductor memory apparatus may include forming a channel region and a gate region through a self-alignment etching process on a cell region; and forming a three-dimensional multi-channel region through an etching process using a first multi-channel mask on a core region and a peripheral region and forming a gate region through an etching process using a second multi-channel mask, thereby preventing mis-arrangement of gates.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: September 27, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Don Lee
  • Method of fabricating semiconductor apparatus having saddle-fin transistor and semiconductor apparatus fabricated thereby
    Patent number: 8012834
    Abstract: A method of fabricating a saddle-fin transistor may include: forming a buffer oxide film and a hard mask oxide film over a semiconductor substrate; etching the buffer oxide film, the hard mask oxide film and the semiconductor substrate corresponding to a mask pattern to form a trench corresponding to a gate electrode and a fin region; oxidizing the exposed semiconductor substrate in the trench to form a gate oxide film; depositing a gate lower electrode in the trench; and depositing a gate upper electrode over the gate lower electrode to fill the trench.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: September 6, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Don Lee
  • Transistor of Volatile Memory Device with Gate Dielectric Structure Capable of Trapping Charges and Method for Fabricating the Same
    Publication number: 20110198701
    Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.
    Type: Application
    Filed: April 26, 2011
    Publication date: August 18, 2011
    Inventors: Sang-Don LEE, Yil-Wook Kim, Jin-Hong Ahn, Young-June Park
  • Semiconductor Memory Apparatus and Method of Operating the Same
    Publication number: 20110149629
    Abstract: A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 23, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sung Bo Shim, Sang Don Lee, Jong Woo Kim
  • Semiconductor device having a recess channel transistor
    Patent number: 7960761
    Abstract: The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate under the active region. A method for fabricating the semiconductor device includes forming a device isolation structure in a semiconductor substrate to form an active region having a recess region at a lower part of sidewalls thereof, a gate insulating film formed over the semiconductor substrate including the recess channel region, and a gate electrode formed over the gate insulating film to fill up the recess channel region.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: June 14, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Woong Chung, Sang Don Lee
  • Apparatus and method for supplying charge voltage to organic photoconductor drum
    Publication number: 20110135328
    Abstract: Provided is an apparatus and method for supplying a charge voltage to an organic photoconductor (OPC) drum. The apparatus includes a storage unit for storing first service life information of the OPC drum according to a first supplying method, and second service life information of the OPC drum according to a second supplying method, a sensor unit for measuring information about conditions surrounding the apparatus, a control unit for selecting one of the first and second supplying methods according to the measured information and determining a charge voltage corresponding to the service life information according to the selected method, and a voltage supplying unit using the selected method to supply the determined charge voltage to the OPC drum.
    Type: Application
    Filed: September 9, 2010
    Publication date: June 9, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung-Kook Ahn, Sang-don Lee, Sung-min Park
  • Semiconductor device with increased channel area and decreased leakage current
    Patent number: 7910989
    Abstract: The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the recess channel region. The gate structure is disposed over the recess channel region of the gate region.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: March 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Woong Chung, Sang Don Lee