Patents by Inventor Sanjeev N. Trika

Sanjeev N. Trika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10831734
    Abstract: An update-insert (“upsert”) interface manages updates to key-value storage at a memory or storage device. An upsert token is used to store a key and data for a transform to update a previous value stored for a key-value pair. The upsert token processing includes an upsert command to generate the upsert token for an existing key-value pair and store the upsert token in one or more first non-volatile memory (NVM) devices maintained at a memory or storage device. A hash-to-physical (H2P) table or index stored in one or more second NVM devices of the memory or storage device is utilized to locate and read the data for the key and the data for the transform and coalesce the transform(s) into a current value for the key-value pair, thereby avoiding unnecessary read and write amplification when updating key-value storage.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Peng Li, Sanjeev N. Trika
  • Publication number: 20200319815
    Abstract: An apparatus comprises a controller comprising an interface comprising circuitry to communicate with a host computing device; and a relocation manager comprising circuitry, the relocation manager to provide, for the host computing device, an identification of a plurality of data blocks to be relocated within a non-volatile memory; and relocate at least a subset of the plurality of data blocks in accordance with a directive provided by the host computing device in response to the identification of the plurality of data blocks to be relocated.
    Type: Application
    Filed: June 16, 2020
    Publication date: October 8, 2020
    Applicant: Intel Corporation
    Inventors: Bishwajit Dutta, Sanjeev N. Trika
  • Patent number: 10761779
    Abstract: Techniques enable offloading operations to be performed closer to where the data is stored in systems with sharded and erasure-coded data, such as in data centers. In one example, a system includes a compute sled or compute node, which includes one or more processors. The system also includes a storage sled or storage node. The storage node includes one or more storage devices. The storage node stores at least one portion of data that is sharded and erasure-coded. Other portions of the data are stored on other storage nodes. The compute node sends a request to offload an operation to the storage node to access the sharded and erasure-coded data. The storage node then sends a request to offload the operation to one or more other storage nodes determined to store one or more codes of the data. The storage nodes perform the operation on the portions of locally stored data and provide the results to the next-level up node.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Steven C. Miller
  • Publication number: 20200264800
    Abstract: An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Inventors: Piotr WYSOCKI, Sanjeev N. TRIKA, Gregory B. TUCKER, Jackson ELLIS, Jonathan M. HUGHES
  • Patent number: 10747439
    Abstract: Power-fail safe compression and dynamic capacity for a storage device in a computer system is provided. Metadata stored with each logical block in non-volatile memory in the storage device ensures that the mapping table may be recovered and stored in volatile memory for use by the computer system after power is restored to the computer system. In addition, the metadata ensures that a list of free logical block addresses written to the storage device prior to shutting down the computer system to provide access to the additional capacity that is available in the storage device by storing compressed data in the storage device may also be recovered.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Rowel S. Garcia, Sanjeev N. Trika, Jawad B. Khan
  • Publication number: 20200249980
    Abstract: Examples include techniques for managing high priority (HP) and low priority (LP) write transaction requests by a storage device. An embodiment includes receiving, at a storage controller for a storage device, a write transaction request from a requestor to write data to one or more memory devices in the storage device. When the write transaction request is for a high priority (HP) write, coalescing the write data into a transaction buffer in a memory of the storage device, sending an acknowledgment for the write transaction request to the requestor, and writing the write data into the one or more memory devices. When the write transaction request is for a low priority (LP) write, writing the write data into the one or more memory devices, and then sending an acknowledgment for the write transaction request to the requestor.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Inventors: Bishwajit DUTTA, Sanjeev N. TRIKA, Anand S. RAMALINGAM, Pallav H. GALA
  • Publication number: 20200226067
    Abstract: An apparatus is described. The apparatus includes a mass storage device processor that is to behave as an additional general purpose processing core of a computing system that a mass storage device having the mass storage device processor is to be coupled to, wherein, the mass storage device processor is to execute out of a component of main memory within the mass storage device.
    Type: Application
    Filed: March 24, 2020
    Publication date: July 16, 2020
    Inventors: Frank T. HADY, Sanjeev N. TRIKA
  • Patent number: 10700703
    Abstract: To address the storage needs of applications that work with noisy data (e.g. image, sound, video data), where errors can be tolerated to a certain extent and performance is more critical than data fidelity, dynamic reliability levels enable storage devices capable of storing and retrieving data with varying degrees of data fidelity to dynamically change the degree of data fidelity in response to an application's request specifying reliability level. By allowing the application to specify the reliability level at which its data is stored and retrieved, dynamic reliability levels can increase read/write performance without sacrificing application accuracy. The application can specify reliability levels for different types or units of data, such as different reliability levels for metadata as opposed to data and so forth.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Sanjeev N. Trika, Omesh Tickoo, Wei Wu
  • Patent number: 10685097
    Abstract: An embodiment of a semiconductor apparatus may include technology to receive an application-related checkpoint request corresponding to a file of a file system stored on a persistent storage media, and determine one or more checkpoint operations internal to the persistent storage media to perform the application-related checkpoint request. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Vadim Sukhomlinov, Sanjeev N. Trika
  • Publication number: 20200174977
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.
    Type: Application
    Filed: January 27, 2020
    Publication date: June 4, 2020
    Inventors: Sanjeev N. TRIKA, Jawad B. KHAN, Piotr WYSOCKI
  • Publication number: 20200117397
    Abstract: Examples herein relate to a storage system that separately handles portions of a write operation that are aligned and misaligned with respect to retrievable segments from a storage device. For misaligned portions, a buffer can be used to store misaligned retrievable segments and update the segments with content provided with the write operation. Aligned portions of content associated with a write request can be written directly to the storage medium or overwrite corresponding retrievable segments present in the buffer. A table or array can track logical block addresses that correspond to content in the buffer or in the storage. Content in the buffer can be kept in the buffer without being backed-up or persisted to the storage until a triggering event occurs such as power loss or low space in the buffer.
    Type: Application
    Filed: December 12, 2019
    Publication date: April 16, 2020
    Inventors: Peng LI, Jawad B. KHAN, Sanjeev N. TRIKA
  • Patent number: 10620870
    Abstract: Embodiments of the present disclosure may relate to a data storage controller that may include a host interface to receive a request from a host to perform a data copy operation on a non-volatile data storage component of a data storage device, where the request identifies one or more source ranges of the non-volatile data storage component from which data is to be copied, a destination range of the non-volatile data storage component to which the data is to be copied, and a transfer length in bytes for each of the one or more source ranges, and a processor coupled with the host interface to process the request from the host to perform the data copy operation to copy the data from the one or more source ranges to the destination range based at least in part on the transfer length in bytes. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Peng Li, Sanjeev N. Trika
  • Patent number: 10606488
    Abstract: In one embodiment, a storage drive is configured to receive a selective flush command which causes the storage drive to selectively flush write data which has been identified in connection with the selective flush command, from volatile buffer memory to a nonvolatile storage memory. Conversely, write data stored in the volatile buffer memory which is not identified in connection with the selective flush command, may remain unaffected by the selective flush command, and thus may remain stored in the volatile buffer memory without being flushed to the nonvolatile storage memory as a result of the selective flush command. Other aspects are described herein.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 31, 2020
    Assignee: INTEL CORPORATION
    Inventor: Sanjeev N. Trika
  • Publication number: 20200097405
    Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 27, 2019
    Publication date: March 26, 2020
    Inventors: Peng Li, Jawad B. Khan, Sanjeev N. Trika
  • Patent number: 10592408
    Abstract: Provided are an apparatus, computer program product, system, and method for managing multiple regions of a non-volatile memory device. A first group of logical bands is assigned to a first memory region in which metadata will be stored and a second group of logical bands is assigned to a second memory region to which host data is written, wherein the second group of logical bands is larger than the first group of logical bands. Physical bands are mapped to the first number of logical bands and the second number of logical bands. Indication is returned to the host system of the first and second groups of logical bands assigned to the first and second memory regions, respectively. The host system directs requests for metadata to logical addresses in the first group of logical bands and directs request for file data to logical addresses in the second group of logical bands.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: March 17, 2020
    Assignee: INTEL CORPORATION
    Inventors: Peng Li, Sanjeev N. Trika
  • Publication number: 20200034304
    Abstract: A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required.
    Type: Application
    Filed: May 7, 2019
    Publication date: January 30, 2020
    Inventor: Sanjeev N. TRIKA
  • Patent number: 10545925
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data, and write data to the at least one storage device.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Jawad B. Khan, Piotr Wysocki
  • Patent number: 10528463
    Abstract: Technologies for combining logical-to-physical address updates include a data storage device. The data storage device includes a non-volatile memory to store data and a logical to physical (L2P) table indicative of logical addresses and associated physical addresses of the data. Additionally, the data storage device includes a volatile memory to store one or more bins. Each bin is indicative of a subset of entries in the L2P table. Further, the data storage device includes a controller to allocate a bin in the volatile memory, write a plurality of updates to a subset of entries of the L2P table to the bin, and write the bin to the L2P table in a single write operation. Other embodiments are also described and claimed.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: Peng Li, Anand S. Ramalingam, William K. Lui, Sanjeev N. Trika
  • Patent number: 10482010
    Abstract: An embodiment of a memory apparatus may include a persistent host memory buffer, and a memory controller communicatively coupled to the persistent host memory buffer to control communication between the persistent host memory buffer and a persistent storage media device. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: James A. Boyd, John W. Carroll, Sanjeev N. Trika
  • Patent number: 10466917
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine prior state information corresponding to one or more of a power state, a system state, a device state, and an operating system state, and load an indirection structure for a persistent storage media in the background based on the prior state information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Myron Loewen, Sanjeev N. Trika