Patents by Inventor Sanjeev N. Trika

Sanjeev N. Trika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190079859
    Abstract: Provided are an apparatus, computer program product, system, and method for managing multiple regions of a non-volatile memory device. A first group of logical bands is assigned to a first memory region in which metadata will be stored and a second group of logical bands is assigned to a second memory region to which host data is written, wherein the second group of logical bands is larger than the first group of logical bands. Physical bands are mapped to the first number of logical bands and the second number of logical bands. Indication is returned to the host system of the first and second groups of logical bands assigned to the first and second memory regions, respectively.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 14, 2019
    Inventors: Peng LI, Sanjeev N. TRIKA
  • Publication number: 20190079681
    Abstract: One embodiment provides a memory controller. The memory controller includes logical block address (LBA) section defining logic to define a plurality of LBA sections for a memory device circuitry, each section including a range of LB As, and each section including a unique indirection-unit (IU) granularity; wherein the IU granularity defines a physical region size of the memory device. The LBA section defining logic also to generate a plurality of logical-to-physical (L2P) tables to map a plurality of LBAs to physical locations of the memory device, each L2P table corresponding to an LBA section. The memory controller also includes LBA section notification logic to notify a file system of the plurality of LBA sections to enable the file system to issue a read and/or write command having an LBA based on an IU granularity associated with an LBA section.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Applicant: Intel Corporation
    Inventors: SANJEEV N. TRIKA, PENG LI, JAWAD B. KHAN
  • Patent number: 10216445
    Abstract: One embodiment provides an apparatus. The apparatus include a device storage logic. The device storage logic is to determine a key-based pointer based, at least in part, on a key included in an input key-value (KV) pair received from a host device and to determine whether a unique input KV data block included in the input KV pair is duplicated in a nonvolatile memory circuitry of a storage device.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Peng Li, Jawad B. Khan, Sanjeev N. Trika, Vinodh Gopal
  • Patent number: 10216415
    Abstract: Provided are a computer program product, system, and method for dynamically increasing capacity of a storage device. For address mappings, each addressing mapping indicates a storage device block address for a host block address and a compressed block size indicating a number of blocks storing compressed data for data written to the host block address starting at the storage device block address. Write data for a write request to a host block address is compressed to produce compressed data. A block size of the compressed data is less than request block size of the write data for the write request. Indication is made in the address mapping for the host block address of a storage device address at which to start storing the compressed data in the storage device and the compressed block size. The compressed data is sent to the storage device to write at the storage device block address.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: February 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Rowel S. Garcia, Sanjeev N. Trika
  • Patent number: 10203888
    Abstract: Technologies for performing a data copy operation on a data storage device include storing a copy token in a power-fail-safe data structure that identifies the source address and destination address of the data copy operation, updating an address table to indicate that the source and destination addresses are involved in the data copy operation, and notifying a host requesting that data copy operation that the data copy operation has been completed prior to performing the data copy operation. The host may subsequently perform other tasks while the data storage device completes the data copy operation. During the data copy operation, data access requests to the source or destination addresses are blocked based on the address table. Additionally, should a power failure event occur, the power-fail-safe data structure is saved to non-volatile data storage so that the copy operation may be completed upon the next power-on event of the data storage device.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Anand S. Ramalingam
  • Publication number: 20190042571
    Abstract: An update-insert (“upsert”) interface manages updates to key-value storage at a memory or storage device. An upsert token is used to store a key and data for a transform to update a previous value stored for a key-value pair. The upsert token processing includes an upsert command to generate the upsert token for an existing key-value pair and store the upsert token in one or more first non-volatile memory (NVM) devices maintained at a memory or storage device. A hash-to-physical (H2P) table or index stored in one or more second NVM devices of the memory or storage device is utilized to locate and read the data for the key and the data for the transform and coalesce the transform(s) into a current value for the key-value pair, thereby avoiding unnecessary read and write amplification when updating key-value storage.
    Type: Application
    Filed: May 7, 2018
    Publication date: February 7, 2019
    Inventors: Peng LI, Sanjeev N. TRIKA
  • Publication number: 20190042460
    Abstract: A computer system that includes a host based byte addressable persistent buffer to store a Logical to Physical (L2P) indirection table for a solid-state drive is provided. Shutdown and startup of the computer system is accelerated by storing the L2P indirection table in the host based byte addressable persistent buffer.
    Type: Application
    Filed: February 7, 2018
    Publication date: February 7, 2019
    Inventors: Sanjeev N. TRIKA, Rowel S. GARCIA
  • Publication number: 20190042153
    Abstract: A mass storage device controller is described. The controller is to process first and second read requests received at an I/O interface of a mass storage device. The first read request includes a first logical block address. The first read request is to provide a first block stored within non volatile storage media of the mass storage device at the I/O interface. The first block is identified by the first logical block address. The second read request includes a second logical block address and specifies one or more bytes within a second block identified by the second block address and stored within the non volatile storage media. The second read request is to provide the one or more bytes at the I/O interface.
    Type: Application
    Filed: December 28, 2017
    Publication date: February 7, 2019
    Inventors: Jawad B. KHAN, Sanjeev N. TRIKA, Myron LOEWEN, Peng LI
  • Publication number: 20190042594
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data, and write data to the at least one storage device.
    Type: Application
    Filed: June 6, 2018
    Publication date: February 7, 2019
    Inventors: Sanjeev N. TRIKA, Jawad B. KHAN, Piotr WYSOCKI
  • Publication number: 20190042355
    Abstract: An apparatus may include a storage driver, the storage driver coupled to a processor, to a non-volatile random access memory (NVRAM), and to a redundant array of independent disks (RAID), the storage driver to: receive a memory write request from the processor for data stored in the NVRAM; calculate parity data from the data and store the parity data in the NVRAM; and write the data and the parity data to the RAID without prior storage of the data and the parity data to a journaling drive. In embodiments, the storage driver may be integrated with the RAID. In embodiments, the storage driver may write the data and the parity data to the RAID by direct memory access (DMA) of the NVRAM.
    Type: Application
    Filed: June 26, 2018
    Publication date: February 7, 2019
    Inventors: Slawomir Ptak, Piotr Wysocki, Kapil Karkra, Sanjeev N. Trika
  • Publication number: 20190042111
    Abstract: Power-fail safe compression and dynamic capacity for a storage device in a computer system is provided. Metadata stored with each logical block in non-volatile memory in the storage device ensures that the mapping table may be recovered and stored in volatile memory for use by the computer system after power is restored to the computer system. In addition, the metadata ensures that a list of free logical block addresses written to the storage device prior to shutting down the computer system to provide access to the additional capacity that is available in the storage device by storing compressed data in the storage device may also be recovered.
    Type: Application
    Filed: March 2, 2018
    Publication date: February 7, 2019
    Inventors: Rowel S. GARCIA, Sanjeev N. TRIKA, Jawad B. KHAN
  • Publication number: 20190042710
    Abstract: An embodiment of a semiconductor apparatus may include technology to receive an application-related checkpoint request corresponding to a file of a file system stored on a persistent storage media, and determine one or more checkpoint operations internal to the persistent storage media to perform the application-related checkpoint request. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 29, 2017
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Vadim Sukhomlinov, Sanjeev N. Trika
  • Publication number: 20190044536
    Abstract: To address the storage needs of applications that work with noisy data (e.g. image, sound, video data), where errors can be tolerated to a certain extent and performance is more critical than data fidelity, dynamic reliability levels enable storage devices capable of storing and retrieving data with varying degrees of data fidelity to dynamically change the degree of data fidelity in response to an application's request specifying reliability level. By allowing the application to specify the reliability level at which its data is stored and retrieved, dynamic reliability levels can increase read/write performance without sacrificing application accuracy. The application can specify reliability levels for different types or units of data, such as different reliability levels for metadata as opposed to data and so forth.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 7, 2019
    Inventors: Jawad B. KHAN, Sanjeev N. TRIKA, Omesh Tickoo, Wei WU
  • Publication number: 20190042152
    Abstract: Examples include techniques for implementing a write transaction to two or more memory devices in a storage device. In some examples, the write transaction includes an atomic write transaction from an application or operating system executing on a computing platform to a storage device coupled with the computing platform. For these examples, the storage device includes a storage controller to receive an atomic multimedia write transaction request to write first data and second data; cause the first data to be stored in a first memory device, and cause the second data to be stored in a second memory device, simultaneously and atomically.
    Type: Application
    Filed: December 6, 2017
    Publication date: February 7, 2019
    Inventors: Sanjeev N. TRIKA, Peng LI, Jawad B. KHAN, Myron LOEWEN
  • Publication number: 20190034088
    Abstract: Embodiments of the present disclosure may relate to a data storage controller that may include a host interface to receive a request from a host to perform a data copy operation on a non-volatile data storage component of a data storage device, where the request identifies one or more source ranges of the non-volatile data storage component from which data is to be copied, a destination range of the non-volatile data storage component to which the data is to be copied, and a transfer length in bytes for each of the one or more source ranges, and a processor coupled with the host interface to process the request from the host to perform the data copy operation to copy the data from the one or more source ranges to the destination range based at least in part on the transfer length in bytes. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 8, 2017
    Publication date: January 31, 2019
    Inventors: PENG LI, SANJEEV N. TRIKA
  • Publication number: 20190034427
    Abstract: Disclosed is a data management system configured to provide a key-value data structure architecture for use with a storage device. The key-value data structure includes a logic tree having a tree-based index and a hash table having a hash-based index. For a ‘scan’ (or range query) operation, the data management system scans the tree-based index to determine which keys exist between two search keys in the tree-based index. For a ‘get’ (e.g., a value request) operation, the data management system applies a hash function to a provided key to determine an index in the hash table by which to retrieve a value that corresponds with the provided key. Other operations (e.g., ‘put’, ‘update’, ‘delete’) may include updating both the tree-based index and the hash-based index. The logic tree stores keys and stores a zero byte-sized value with each of the keys, to limit the size of the logic tree.
    Type: Application
    Filed: December 28, 2017
    Publication date: January 31, 2019
    Applicant: Intel Corporation
    Inventors: Sanjeev N. Trika, Dongchul Park, Peng Li, Francis R. Corrado, Robert A. Dickinson
  • Publication number: 20190004940
    Abstract: An embodiment of a memory apparatus may include a persistent host memory buffer, and a memory controller communicatively coupled to the persistent host memory buffer to control communication between the persistent host memory buffer and a persistent storage media device. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Inventors: James A. Boyd, John W. Carroll, Sanjeev N. Trika
  • Publication number: 20190004726
    Abstract: One embodiment provides an apparatus. The apparatus include a device storage logic. The device storage logic is to determine a key-based pointer based, at least in part, on a key included in an input key-value (KV) pair received from a host device and to determine whether a unique input KV data block included in the input KV pair is duplicated in a nonvolatile memory circuitry of a storage device.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Applicant: Intel Corporation
    Inventors: PENG LI, JAWAD B. KHAN, SANJEEV N. TRIKA, VINODH GOPAL
  • Publication number: 20190004947
    Abstract: One embodiment provides host device. The host device includes a host processor circuitry; a host memory circuitry, and a host storage logic to determine whether a data to be stored is temporary or persistent and to provide a write (Write) command associated with the data to a storage device, if the data is persistent data, or to provide a volatile write (vWrite) command associated with the data to the storage device, if the data is temporary data. Another embodiment provides a storage device. The storage device includes a device processor circuitry; a volatile memory circuitry; a nonvolatile memory circuitry; and a device storage logic to store a persistent data to the nonvolatile memory circuitry in response to a write (Write) command from a host device and a temporary data to the volatile memory circuitry in response to a volatile write (vWrite) command from the host device.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Applicant: Intel Corporation
    Inventor: SANJEEV N. TRIKA
  • Publication number: 20190004715
    Abstract: In one embodiment, a storage drive is configured to receive a selective flush command which causes the storage drive to selectively flush write data which has been identified in connection with the selective flush command, from volatile buffer memory to a nonvolatile storage memory. Conversely, write data stored in the volatile buffer memory which is not identified in connection with the selective flush command, may remain unaffected by the selective flush command, and thus may remain stored in the volatile buffer memory without being flushed to the nonvolatile storage memory as a result of the selective flush command. Other aspects are described herein.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventor: Sanjeev N. TRIKA