Patents by Inventor Sanjeev N. Trika

Sanjeev N. Trika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190324683
    Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.
    Type: Application
    Filed: June 29, 2019
    Publication date: October 24, 2019
    Inventors: Peng LI, Jawad B. KHAN, Sanjeev N. TRIKA
  • Publication number: 20190310776
    Abstract: An apparatus is described. The apparatus includes peer-to-peer intelligence to be integrated into a mass storage system having a cache and a backing store. The peer-to-peer intelligence is to move data between the cache and backing store without the data passing through main memory.
    Type: Application
    Filed: May 28, 2019
    Publication date: October 10, 2019
    Inventors: Knut S. GRIMSRUD, Sanjeev N. TRIKA
  • Patent number: 10437731
    Abstract: In embodiments, apparatuses, methods and storage media associated with a multi-level cache are described. A first storage level may receive an input/output (I/O) request from a second storage level of the multi-level cache, wherein the I/O request is associated with a data. The first storage level may further receive an indicator to indicate whether the data is stored or will be stored in the second storage level. The first storage level may determine whether to store the data in the first storage level based on the indicator. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Slawomir Putyrski
  • Patent number: 10430333
    Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 1, 2019
    Inventors: Peng Li, Jawad B. Khan, Sanjeev N. Trika
  • Patent number: 10417218
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receiving a sequence of transactions, each transaction including a request to write data to a memory device, processing the sequence of transactions, and communicating a response to a host after the sequence of transaction have been completed.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: September 17, 2019
    Assignee: INTEL CORPORATION
    Inventors: Kshitij A. Doshi, Sanjeev N. Trika, Sridharan Sakthivelu
  • Patent number: 10416900
    Abstract: Technologies for addressing data in a memory include an apparatus that includes a memory and a controller. The memory is to store sub-blocks of data in a data table and a pointer table of locations of the sub-blocks in the data table. The controller is to manage the storage and lookup of data in the memory. Further, the controller is to store a sub-block pointer in the pointer table to a location of a sub-block in the data table and store a second pointer that references an entry where the sub-block pointer is stored in the pointer table.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Vinodh Gopal, Sanjeev N. Trika
  • Patent number: 10409500
    Abstract: One embodiment provides a memory controller. The memory controller includes logical block address (LBA) section defining logic to define a plurality of LBA sections for a memory device circuitry, each section including a range of LBAs, and each section including a unique indirection-unit (IU) granularity; wherein the IU granularity defines a physical region size of the memory device. The LBA section defining logic also to generate a plurality of logical-to-physical (L2P) tables to map a plurality of LBAs to physical locations of the memory device, each L2P table corresponding to an LBA section. The memory controller also includes LBA section notification logic to notify a file system of the plurality of LBA sections to enable the file system to issue a read and/or write command having an LBA based on an IU granularity associated with an LBA section.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Peng Li, Jawad B. Khan
  • Patent number: 10365844
    Abstract: Provided are an apparatus, method, and system for logical block address to physical block address (L2P) compression. In response to a physical block address (PBA) of a first indirection unit (IU) among a plurality of IUs in a compression unit being updated, it is determined whether IU data of the plurality of IUs is compressible. In response to determining that the IU data is compressible, one or more contiguous IU groups in the compression unit that are compressible are identified based on corresponding PBAs and, then, a compression unit descriptor and PBAs for unique IUs of the plurality of IUs are written into the compression unit. In response to determining that the IU data is incompressible, a flag indicating that IU data is incompressible, PBAs for some of the IUs, and a pointer to PBAs of remaining IUs are written into the compression unit.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 30, 2019
    Assignee: INTEL CORPORATION
    Inventors: Peng Li, Sanjeev N. Trika
  • Publication number: 20190196907
    Abstract: In one example, uncompressed data is compressed and divided into chunks. Each chunk of the compressed data stream is combined with state information to enable each chunk to be independently decompressed. Each of the compressed chunks is then stored on a different storage device along with its associated state information. A compute operation can then be offloaded to the device or node where each chunk is stored. Each chunk can be independently decompressed for execution of the offloaded operation without transferring all chunks to a central location for decompression and performance of the operation.
    Type: Application
    Filed: March 5, 2019
    Publication date: June 27, 2019
    Inventors: Jawad B. KHAN, Sanjeev N. TRIKA
  • Patent number: 10296224
    Abstract: Provided are an apparatus, system and method for using a validity table indicating whether physical addresses have valid data to optimize write and defragmentation operations. A non-volatile memory storage device has non-volatile memory and a main memory. A memory controller reads and writes to the non-volatile memory and maintains in the main memory a logical-to-physical address table indicating, for each logical address of a plurality of logical addresses, a physical address in the non-volatile memory having data for the logical address. The main memory maintains a validity table indicating for each physical address of a plurality of physical addresses in the non-volatile memory whether the physical address has valid data.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Peng Li, William K. Lui, Sanjeev N. Trika
  • Patent number: 10289556
    Abstract: A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventor: Sanjeev N. Trika
  • Publication number: 20190114096
    Abstract: An apparatus is described. The apparatus includes a storage system management unit to manage a storage system having physical storage resources divided into different reliability zones. A data item to be stored in the storage system is to be assigned a particular reliability level by the management unit and is to be stored by the management unit in one of the reliability zones that is to provide a level of protection against data loss that is at least as protective as the particular reliability level.
    Type: Application
    Filed: December 7, 2018
    Publication date: April 18, 2019
    Inventor: Sanjeev N. TRIKA
  • Publication number: 20190114108
    Abstract: Techniques for offloading operations to access data that is compressed and distributed are disclosed. In one example, a system includes a compute node and a storage node. For example, one or more racks in a data center can include compute and storage nodes. The compute node including one or more processors. The storage node includes one or more storage devices to store a portion of compressed data. Other portions of the compressed data are stored on other nodes. The compute node sends a request to the storage node storing the first chunk of compressed data. The storage node receives the request, decompresses at least part of the portion of the compressed data, and performs the operation on the decompressed part. The storage node can then provide a result from the operation to the compute node. Any part of the compressed data that could not be decompressed by the storage node can be sent to the next storage node.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 18, 2019
    Inventors: Sanjeev N. TRIKA, Jawad B. KHAN
  • Publication number: 20190114114
    Abstract: Techniques enable offloading operations to be performed closer to where the data is stored in systems with sharded and erasure-coded data, such as in data centers. In one example, a system includes a compute sled or compute node, which includes one or more processors. The system also includes a storage sled or storage node. The storage node includes one or more storage devices. The storage node stores at least one portion of data that is sharded and erasure-coded. Other portions of the data are stored on other storage nodes. The compute node sends a request to offload an operation to the storage node to access the sharded and erasure-coded data. The storage node then sends a request to offload the operation to one or more other storage nodes determined to store one or more codes of the data. The storage nodes perform the operation on the portions of locally stored data and provide the results to the next-level up node.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 18, 2019
    Inventors: Sanjeev N. TRIKA, Steven C. MILLER
  • Publication number: 20190107976
    Abstract: An apparatus is described. The apparatus includes velocity assignment logic to assign a velocity to data that is to be written to a non volatile storage medium. The velocity assignment logic is to accept input information pertaining to an identity of an application that is writing the data, the data type of the data and the state of the application in order to determine the velocity.
    Type: Application
    Filed: December 7, 2018
    Publication date: April 11, 2019
    Inventor: Sanjeev N. TRIKA
  • Publication number: 20190108137
    Abstract: An intelligent journal-aware caching manager for journaled data is provided. The caching manager ensures that data is not duplicated in a write-ahead-log (“journal”) and volatile cache memory (“cache”). The caching manager maintains first-in-first-out (“FIFO”) policy for the journal as needed and includes an alternate caching policy for non-journaled data.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 11, 2019
    Inventors: Madhurima RAY, Sanjeev N. TRIKA
  • Publication number: 20190102096
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine prior state information corresponding to one or more of a power state, a system state, a device state, and an operating system state, and load an indirection structure for a persistent storage media in the background based on the prior state information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Myron Loewen, Sanjeev N. Trika
  • Publication number: 20190102262
    Abstract: A storage controller performs continuous checkpointing. With continuous checkpointing, the information necessary for system rollback is continuously recorded without the need of a specific command. With the rollback information, the system can rollback or restore to any previous state up to a number of previous writes or up to an amount of data. The number of writes or the amount of data that can be restored are configurable.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Vadim SUKHOMLINOV, Kshitij A. DOSHI, Tamir D. MUNAFO, Sanjeev N. TRIKA, Urvi PATEL, Rowel S. GARCIA
  • Publication number: 20190102293
    Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Peng Li, Jawad B. Khan, Sanjeev N. Trika
  • Patent number: 10248343
    Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Jason B. Akers, Knut S. Grimsrud, Robert J. Royer, Jr., Richard P. Mangold, Sanjeev N. Trika