Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: A mechanically and piezoelectrically anisotropic polymer article is formed from a crystallizable fluoropolymer and a nucleating agent. The polymer article may be a thin film or a fiber, for example. A crystalline phase may constitute at least approximately 50% of the polymer article. In certain examples, a fluoropolymer may include vinylidene fluoride, trifluoroethylene, chlorotrifluoroethylene, hexafluoropropylene, and vinyl fluoride. The polymer article may include up to approximately 10 wt. % of the nucleating agent. Such a polymer article is optically transparent, has an elastic modulus of at least approximately 3 GPa, and an electromechanical coupling factor (k31) of at least approximately 0.15.

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

Abstract: A field-of-view stitching system including: a light source module for emitting a first beam; a light guiding element for splitting the first beam into a plurality of second beams and includes an incident surface, a first exit surface, and a plurality of second exit surfaces, the second beams propagate along an optical path of the first beam; and a plurality of light modulators, a number of the plurality of light modulators is the same as a total number of the first exit surface and the plurality of second exit surfaces, each of the plurality of light modulators is configured to receive and regularly reflect one of the plurality of second beams; the light guiding element is further configured to receive and combine the second beams reflected by the light modulators to form an illuminating light. A field-of-view stitching method, a biological sample identification device and method are also provided.

Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.

Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: A micro light-emitting diode display panel includes a substrate, at least one light-emitting element, a reflective layer and a light-absorbing layer. The at least one light-emitting element is disposed on the substrate to define at least one pixel, and each light-emitting element includes micro light-emitting diodes. The reflective layer is disposed on the substrate and located between the micro light-emitting diodes. The reflective layer has cavities surrounding the micro light-emitting diodes, such that a thickness of a portion of the reflective layer close to any one of the micro light-emitting diodes is greater than a thickness of a portion of the reflective layer away from the corresponding micro light-emitting diode. The light-absorbing layer is at least disposed in the cavities of the reflective layer.

Abstract: An apparatus is disclosed that implements interference and/or clutter cancellation using cross-channel equalization. In example aspects, the apparatus includes a wireless transceiver configured to be connected to multiple feed ports. The wireless transceiver is also configured to transmit an electromagnetic signal using a first feed port of the multiple feed ports. A modulated spur is generated based on the transmission of the electromagnetic signal. The wireless transceiver is additionally configured to receive two versions of a receive signal respectively via two feed ports of the multiple feed ports. The receive signal comprises the modulated spur and a mutual-coupling component associated with the transmission of the electromagnetic signal. The wireless transceiver is further configured to generate a filtered signal by attenuating the mutual-coupling component and the modulated spur within one of the two versions of the receive signal using cross-channel equalization.

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

Abstract: A multilayer polymer thin film includes an anti-reflective coating directly overlying a reflective polarizer stack. The reflective polarizer stack includes alternating first and second polymer layers, where the first layers include an isotropic polymer thin film and the second layers include an anisotropic polymer thin film. The anti-reflective coating (ARC) includes alternating third and fourth layers, where the third layers include an isotropic polymer thin film or an anisotropic polymer thin film and the fourth layers include an isotropic polymer thin film. The multilayer polymer thin film may be formed by co-extrusion where the reflective polarizer stack and the anti-reflective coating are formed simultaneously.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: A micro-light-emitting diode chip includes an epitaxial structure, an electrode, a transparent structure, and a reflection layer. The epitaxial structure has a light exit surface, a back surface opposite to the light exit surface, and a sidewall surface. The sidewall surface is connected to the light exit surface and the back surface. The electrode is electrically coupled to the epitaxial structure. The transparent structure has an inner surface and an outer surface opposite to the inner surface. The inner surface is connected to the sidewall surface. A distance between the outer surface and the inner surface on a plane where the back surface is located is less than a distance between the outer surface and the inner surface on a plane where the light exit surface is located. The reflection layer is in direct contact with the outer surface. A micro-light-emitting diode display is also provided.

Abstract: A data storage device, and an error tolerance selecting method thereof which includes: writing data to data blocks of the data storage device; reading written data of the data blocks as read data; comparing the read data and the written data of each data column in the data blocks, and calculating a number of error bits in each chunk including a plurality of data columns accordingly; calculating a difference value between the number of error bits in the chunk and a first threshold value to store the difference value in an error tolerance list; and selecting a largest difference value in the error tolerance list as an error tolerance.

Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for dynamic tone mapping of video content. An example embodiment operates by identifying, by a dynamic tone mapping system executing on a media device, characteristics of a first video signal having a first dynamic range based on a frame-by-frame analysis of the first video signal. The example embodiment further operates by modifying, by the dynamic tone mapping system, a tone mapping curve based on the characteristics of the first video signal to generate a modified tone mapping curve. Subsequently, the example embodiment operates by converting, by the dynamic tone mapping system, the first video signal based on the modified tone mapping curve to generate a second video signal having a second dynamic range that is less than the first dynamic range.

Abstract: A semiconductor structure includes a substrate and a stack of p-n junction structures embedded in the substrate. The semiconductor structure includes a semiconductor fin protruding from the substrate. The semiconductor structure includes a pair of source/drain structures disposed in the semiconductor fin. The semiconductor structure includes a gate structure over a channel region of the semiconductor fin and interposed between the pair of source/drain structures.

Abstract: A selectable-repairing micro light emitting diode display is provided. A backplane includes a plurality of transistor units. A plurality of pixel units are disposed on the backplane, and each of the pixel units includes a plurality of original sub-pixel units and at least one selectable-repairing sub-pixel unit. Each of the original sub-pixel units includes a set of original pad. The set of original pad is disposed on the backplane and connected to one of the transistor units. The at least one selectable-repairing sub-pixel unit is arranged between two of the original sub-pixel units next to each other and having different colors, and includes a set of repairing pad. The set of repairing pad is not connected to the transistor units. A plurality of micro light emitting elements are electrically connected to the sets of original pad and controlled to emit light through the corresponding transistor units, respectively.