Abstract: A high-speed connector includes an insulating housing, and a first terminal assembly mounted in the insulating housing. The first terminal assembly includes a plurality of first terminals, a first base body and a first conductive film. The plurality of the first terminals include at least two first grounding terminals and at least two first signal terminals. At least one portion of a bottom of the first base body extends downward to form at least one first protruding portion. The at least two first signal terminals penetrate through the at least one first protruding portion. The first conductive film is covered to the at least one first protruding portion. The first conductive film has a first metal layer. The first metal layer is electrically connected with the at least two first grounding terminals to form a grounding structure.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

Abstract: A connect structure for semiconductor processing equipment includes a housing configured to mate a deformable pipe with a non-deformable pipe. The housing includes a first annular sidewall to receive the deformable pipe and a second annular sidewall defining a first thread structure. An annular bead is connected to the first annular sidewall to flexibly deform the deformable pipe toward the non-deformable pipe structure when the first thread structure rotatably engages a second thread structure of the non-deformable pipe.

Abstract: A selecting bad data column method suitable for a data storage device is provided. The data storage device includes a control unit and a data storage medium. The selecting method performed by the control unit includes: reading written data of each data column as read data; comparing the read data and the written data of each data column to calculate an average number of error bits of each data column; determining whether the average number of error bits of each data column is greater than or equal to a predetermined value; and recording a data column as a bad data column when the average number of error bits of the data column is greater than or equal to the predetermined value. In this way, in order to avoid the problems that the error correction code can't be corrected or the correction capability is excessively consumed.

Abstract: A one-time programmable memory structure comprises: A transistor includes a gate. A capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is disposed on the first electrode. A top surface of the first electrode and a top surface of the gate are located on a same plane perpendicular to a direction of the first electrode toward the second electrode. An interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode. A resistor comprises a conductive layer. Top and bottom surfaces of the conductive layer are respectively located on a same plane, perpendicular to the direction of the first electrode toward the second electrode, with the top and bottom surfaces of the gate.

Abstract: A feed detection apparatus of a 3D printer, comprising a gear, a measurement device, a support, and a compression assembly. The gear is provided on the support to abut against a filament material, and rotates along with a movement of the filament material. The measurement device is placed on the support to measure a rotating speed of the gear, and determines a feeding status of the filament material according to a measurement result. The compression assembly comprises a connection member and an abutment member; the connection member is provided between the support and the abutment member; the abutment member is used for regulating a pressure of the connecting member applied on the support so as to enable the gear to abut against the filament material.

Abstract: A bonding tool includes a gas supply line that may extend directly between valves associated with one or more gas supply tanks and a processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks. The pressure in the gas supply line may be maintained at or near the pressure in the processing chamber so that gas provided to the processing chamber through the gas supply line does not cause a pressure imbalance in the processing chamber, which might otherwise cause early or premature contact between semiconductor substrates that are to be bonded in the processing chamber.

Abstract: A composition for protecting liver, protecting intestines and enhancing immunity for freshwater fish is disclosed, including the following raw materials in parts by weight: 15˜27 parts of Andrographis herba, 18˜22 parts of Isatidis folium, 10˜15 parts of Polygonum hydropiper, 8˜12 parts of Rheum palmatum L., and 8˜12 parts of Galla chinensis. And the preparation and the application of the composition are disclosed. The composition of the disclosure has the effect of resisting bacteria, scavenge free radicals, clearing heat, detoxifying, preventing and treating enteritis and the like, which can effectively improve the immunity of the freshwater fish and ensure the health of the organism.

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

Abstract: A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: An image processing system and a processing method of video stream are provided. The first image is obtained according to a parameter. The deformation correction procedure is performed on the first image, and the second image is generated. The identification detection procedure is performed on the second image, and a detected result is generated. Control information is generated according to the detected result. The parameter is adjusted according to the control information, and a third image is generated. The second image and the third image are output. Therefore, the subsequent application could be enhanced through the dual image outputs.

Abstract: An electrical connector includes an insulating housing, an upper terminal assembly fastened in the insulating housing, a center grounding plate fastened in the insulating housing, and an outer shell disposed to a top surface of the insulating housing. A rear end of the insulating housing has two first penetrating grooves. The upper terminal assembly includes an upper base portion. A rear end of the upper base portion defines two second penetrating grooves. The two second penetrating grooves are aligned with the two first penetrating grooves. Two opposite sides of a rear end of a top surface of the outer shell extend towards the insulating housing to form two elastic arms, respectively. The two elastic arms pass through the two first penetrating grooves and the two second penetrating grooves, and then the two elastic arms contact with two outermost upper grounding terminals of the upper terminal assembly.

Abstract: A selectable-repairing micro light emitting diode display is provided. A backplane includes a plurality of transistor units. A plurality of pixel units are disposed on the backplane, and each of the pixel units includes a plurality of original sub-pixel units and at least one selectable-repairing sub-pixel unit. Each of the original sub-pixel units includes a set of original pad. The set of original pad is disposed on the backplane and connected to one of the transistor units. The at least one selectable-repairing sub-pixel unit is arranged between two of the original sub-pixel units next to each other and having different colors, and includes a set of repairing pad. The set of repairing pad is not connected to the transistor units. A plurality of micro light emitting elements are electrically connected to the sets of original pad and controlled to emit light through the corresponding transistor units, respectively.

Abstract: A display panel includes a pixel unit. The pixel unit includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first light-emitting element, a first light source element, and a first color conversion structure. A light emitted by the first light-emitting element has a first color. The first color conversion structure is disposed on the first light source element and adapted to convert a light emitted by the first light source element into a light of the first color. The second sub-pixel includes a second light-emitting element. A light emitted by the second light-emitting element has a second color different from the first color.

Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, forming a first doped region adjacent to the STI, removing part of the STI, and then forming a first gate structure on the substrate and the STI. Preferably, the first gate structure includes a high-k dielectric layer on the substrate and a gate electrode on the high-k dielectric layer, in which the high-k dielectric layer comprises a first L-shape.

Abstract: The present disclosure provides, the semiconductor device includes a substrate, a first transistor, a capacitor, and two first plugs. The substrate has a high-voltage region and a capacitor region. The first transistor is disposed in the high-voltage region, and includes a first gate dielectric layer, a first gate electrode, and a first capping layer. The capacitor is disposed in the capacitor region and includes a second gate electrode, a second capping layer, a dielectric layer, and a conductive layer. The two first plugs are disposed on the capacitor, wherein one of the two first plugs penetrates through the second capping layer to directly contact the second gate electrode, and another one of the two first plugs directly contacts the conductive layer.