Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a first mesa isolation on the HEMT region and a second mesa isolation on the capacitor region, forming a HEMT on the first mesa isolation, and then forming a capacitor on the second mesa isolation.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless device may transmit a frequency-modulated continuous-waveform (FMCW) dual ramp radar signal over a time duration that sweeps from a first frequency to a second frequency and from the second frequency to the first frequency. The wireless device may receive a reflection of the radar signal with a first reflected part that corresponds to the first part of the radar signal and a second reflected part that corresponds to the second part of the radar signal. The wireless device may compare the first reflected part and a time-inverted version of the second reflected part to estimate a noise pattern. The wireless device may perform an action based at least in part on the noise pattern. Numerous other aspects are described.

Abstract: A curved panel includes a first curved substrate, a second curved substrate, a curved coverlens, and an adhesive structure. The first curved substrate and the second curved substrate are overlapped with each other. First to fourth sidewalls of the first curved substrate correspond to fifth to eighth sidewalls of the second curved substrate, respectively. The first to third sidewalls of the first curved substrate extend beyond the fifth to seventh sidewalls of the second curved substrate, respectively. The second curved substrate is located between the curved coverlens and the first curved substrate. The second curved substrate is bonded to the curved coverlens through an adhesive layer. The adhesive structure is located between the first curved substrate and the curved coverlens and is laterally located between the first sidewall and the fifth sidewall, between the second sidewall and the sixth sidewall, and between the third sidewall and the seventh sidewall.

Abstract: A preclean process may be omitted from a eutectic bonding sequence. To remove oxide from one or more surfaces of a device wafer of a micro-electromechanical-system (MEMS) structure, a duration of an acid-based etch process in the eutectic bonding sequence may be increased relative to the duration of the acid-based etch process when the preclean process is performed. The increased duration of the acid-based etch process enables the acid-based etch process to remove the oxide from the one or more surfaces of the device wafer without the use of a preceding preclean process. This reduces the complexity and cycle time of the eutectic bonding sequence, reduces the risk of stiction between suspended mechanical components of the MEMS structure, and/or reduces the likelihood that the MEMS structure may be rendered defective or inoperable during manufacturing, which increases process yield.

Abstract: An integrated circuit chip has an active surface and a chip pad arrangement on the active surface. The chip pad arrangement includes four pairs of chip pads arranged in two rows along a side edge of the active surface. Two pairs of chip pads are a first transmission differential pair chip pad and a first reception differential pair chip pad respectively. Positions of the two pairs of chip pads are not adjacent to each other and are in different rows. The other two pairs of chip pads are a second transmission differential chip pad and a second reception differential chip pad respectively. Positions of the other two pairs of chip pads are not adjacent to each other and are in different rows. In addition, a package substrate corresponding to the integrated circuit chip and an electronic assembly including the package substrate and the integrated circuit chip are also provided.

Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for dynamic tone mapping of video content. An example embodiment operates by identifying, by a dynamic tone mapping system executing on a media device, characteristics of a first video signal having a first dynamic range based on a frame-by-frame analysis of the first video signal. The example embodiment further operates by modifying, by the dynamic tone mapping system, a tone mapping curve based on the characteristics of the first video signal to generate a modified tone mapping curve. Subsequently, the example embodiment operates by converting, by the dynamic tone mapping system, the first video signal based on the modified tone mapping curve to generate a second video signal having a second dynamic range that is less than the first dynamic range.

Abstract: A method for manufacturing a memory device includes forming a first metal layer over a substrate, forming a magnetic tunnel junction (MTJ) layer stack over the first metal layer, forming a second metal layer over the MTJ layer stack, forming a hard mask layer over the second metal layer, performing a first etching process on the MTJ layer stack to form an MTJ structure and a redeposited layer on a sidewall of the MTJ structure, performing a second etching process to remove the redeposited layer, and performing a third etching process on the sidewall of the MTJ structure.

Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.

Abstract: In some aspects, a radar device may receive a plurality of received signals comprising a plurality of reflected frequency modulated continuous wave radar signals and phase noise. The radar device may obtain a frequency-domain representation of the received signals comprising a plurality of frequency-domain spectrums. The radar device may determine a shaped noise component of the frequency-domain representation corresponding to a negative distance portion of the frequency-domain representation. The radar device may determine a shaped decision boundary for target detection based at least in part on the shaped noise component, wherein the shaped decision boundary corresponds to a positive distance portion of the frequency-domain representation. The radar device may detect a radar target based at least in part on the shaped decision boundary. The radar device may perform an action based at least in part on detecting the radar target. Numerous other aspects are described.

Abstract: A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.

Abstract: A micro light-emitting diode display device includes a display substrate, multiple pixels, and at least one color conversion layer. The pixels are disposed on the display substrate. Each of the pixels includes multiple sub-pixels. Each of the sub-pixels includes at least one micro light-emitting diode. The at least one color conversion layer is disposed on the pixels. The at least one color conversion layer is continuously disposed on at least a part of sub-pixels of different pixels along a same direction.

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. A fluoride ion doped region is formed right below the main gate in the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

Abstract: A micro LED display device including a display substrate, a plurality of conductive pad pairs and a plurality of micro light emitting elements is provided. The display substrate has a first arranging area, a splicing area connected to the first arranging area, and a second arranging area connected to the splicing area, wherein the splicing area is located between the first arranging area and the second arranging area. The conductive pad pairs are disposed on the display substrate in an array with the same pitch. The micro light emitting elements are disposed on the display substrate and are electrically bonded to the conductive pad pairs. A manufacturing method of the micro LED display device is also provided.

Abstract: A resistor with GaN structures, including a GaN layer with a 2DEG resistor region and an undoped polysilicon resistor region, an AlGaN barrier layer on the GaN layer in the 2DEG resistor region, multiple p-type doped GaN capping layers arranged on the AlGaN barrier layer so that the GaN layer not covered by the p-type doped GaN capping layers in the 2DEG resistor region is converted into a 2DEG resistor, a passivation layer on the GaN layer, and an undoped polysilicon layer on the passivation layer in the undoped polysilicon resistor region and functions as an undoped polysilicon resistor.

Abstract: A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.

Abstract: A multilayer-type on-chip inductor includes a first winding portion arranged in an inter-metal dielectric (IMD) layer, which includes first and second semi-circular stacking layers arranged from inside to outside and in concentricity. A second winding portion includes third and fourth semi-circular stacking layers arranged symmetrically with the first semi-circular stacking layer and the second semi-circular stacking layer, respectively, with respect to a symmetry axis. A conductive branch layer is disposed in an insulating redistribution layer over the IMD layer. The first, second, third, and fourth semi-circular stacking layers each include an uppermost trace layer and a next uppermost trace layer vertically stacked under the uppermost trace layer.

Abstract: A wafer pod transfer assembly includes a wafer pod port to receive a wafer pod, a transfer axle coupled to the wafer pod port, a shaft receiver, a shaft coupled to the transfer axle and to the shaft receiver, a pin through the shaft receiver and through the shaft, wherein the pin comprises a first end and a second end, opposite the first end, and a pin buckle including a first loop and a second loop. The pin buckle is coupled to the pin, the first loop encircles the first end of the pin, and the second loop encircles the second end of the pin.

Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.

Abstract: The present application provides a solid metal material quickly soluble in water, comprising components of magnesium, gadolinium, yttrium, praseodymium, neodymium, platinum, hafnium, nickel, potassium, and manganese in a specific proportion. Furthermore, the solid metal material quickly soluble in water further comprises aluminum, copper, calcium, iron, zinc, and sodium. The present application also provides a preparation method for the solid metal material quickly soluble in water. The solid metal material quickly soluble in water provided by the present application is a quickly soluble magnesium alloy material capable of adapting to the waiting time requirement of the public for washing, can be hydrolyzed, and can react with water in a washing machine, and is environmentally friendly. Washing substances remaining on the clothes have no irritation to human skin contact, and the washing and discharging sewage discharged after washing has no harm to the environment.

Abstract: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer correspondingly formed below the first spiral trace layer, wherein the inter-metal dielectric layer has a separating region to divide the second spiral trace layer into a plurality of line segments, and wherein each of a plurality of first slit openings and each of a plurality of second slit openings pass through a corresponding line segment, and extend in an extending direction of a length of the corresponding line segment.