Patents by Inventor Sheng Yuan

Sheng Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11532666
    Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle, a top view of the first metal interconnection includes a flat oval overlapping the circle, and the MTJ includes a bottom electrode, a fixed layer, a free layer, a capping layer, and a top electrode.
    Type: Grant
    Filed: March 21, 2021
    Date of Patent: December 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ting-Hsiang Huang, Yi-Chung Sheng, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Chih-Kai Kang
  • Publication number: 20220395831
    Abstract: A method herein to isolate exosomes includes providing a microfluidic device having a spiral-shaped channel in fluid communication with two inlet ports and at least two outlet ports. One of the two inlet ports is proximal to an inner wall of the spiral-shaped channel and the other is proximal to an outer wall thereof. At least one of the outlet ports is in fluid communication with a container for storing isolated exosomes. A blood sample and sheath fluid are introduced into the inlet ports proximal to the outer and inner walls, respectively, to form a diluted sample in the spiral-shaped channel and driven through for exosomes recovery in the container. The spiral-shaped channel in fluid communication with a first outlet port includes a first outlet channel connecting the spiral-shaped channel to the first outlet port and is longer than other outlet channels respectively connecting the spiral-shaped channel to the other outlet ports. A method of identifying diabetes mellitus is also disclosed herein.
    Type: Application
    Filed: October 21, 2020
    Publication date: December 15, 2022
    Inventors: Han Wei HOU, Hui Min TAY, Sheng Yuan LEONG
  • Publication number: 20220392905
    Abstract: A method for fabricating an one time programmable (OTP) device includes the steps of: forming a first gate structure and a second gate structure extending along a first direction on a substrate; forming a diffusion region adjacent to two sides of the first gate structure and the second gate structure; forming a silicide layer adjacent to the first gate structure; and patterning the first gate structure for forming a third gate structure and a fourth gate structure.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 8, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Chih-Wei Yang, Chang-Chien Wong, Te-Wei Yeh, Sheng-Yuan Hsueh
  • Publication number: 20220386469
    Abstract: A twistable electronic device module including a twistable substrate, an electrode pattern layer, an insulating layer, a circuit layer, a plurality of circuit boards and a plurality of electronic devices is provided. The electrode pattern layer is disposed on the twistable substrate. The insulating layer is disposed on the electrode pattern layer. The edge of the insulating layer has an opening located at the edge of the twistable substrate and exposing a part of the electrode pattern layer. The circuit layer is disposed on the insulating layer and on the sidewall of the opening, and is connected with the electrode pattern layer. The plurality of circuit boards are disposed on the circuit layer, and each is electrically connected to the circuit layer.
    Type: Application
    Filed: July 16, 2021
    Publication date: December 1, 2022
    Applicant: National Taipei University of Technology
    Inventors: Syang-Peng Rwei, Tzu-Wei Chou, Sheng-Yuan Huang
  • Publication number: 20220384521
    Abstract: Structures and formation methods of a semiconductor structure are provided. The semiconductor structure includes an insulating layer covering a device region and an alignment mark region of a semiconductor substrate. A conductive feature is formed in the insulating layer and corresponds to the device region. An alignment mark structure is formed in the first insulating layer and corresponds to the alignment mark region. The alignment mark structure includes a first conductive layer, a second conductive layer covering the first conductive layer, and a first magnetic tunnel junction (MTJ) stack layer covering the second conductive layer. The first conductive layer and the conductive feature are made of the same material.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Inventors: Wei-De HO, Lan-Hsin CHIANG, Chien-Hua HUANG, Chung-Te LIN, Yung-Yu WANG, Sheng-Yuan CHANG, Kai-Chieh LIANG
  • Publication number: 20220365103
    Abstract: The present invention provides methods and compositions, e.g., kits, for assaying a vitamin D moiety in a sample, comprising or using, inter alia, a buffer that is capable of dissociating a vitamin D moiety from its binding protein and/or a buffer of acidic pH, and at least two antibodies, e.g., at least two monoclonal antibodies, that are separately conjugated to particles, e.g., latex particles, wherein at least one of said antibodies (or the first antibody) has a specific binding affinity towards the vitamin D moiety, and at least another said antibody (or the second antibody) has a specific binding affinity towards the complex formed between the first antibody and the vitamin D moiety, if present in said sample. In some embodiments, the optical change due to the agglutination reaction between the antibodies and the vitamin D moiety is measured for determination of the amount of vitamin D content in the samples. Kits and reaction mixtures for assaying a vitamin D moiety in a sample are also provided.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Applicant: Diazyme Laboratories, Inc.
    Inventors: Chong-Sheng YUAN, Kakhri Ben Habib SAIDA
  • Publication number: 20220365424
    Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Kuo-Hao LEE, You-Cheng JHANG, Han-Zong PAN, Jui-Chun WENG, Chiu-Hua CHUNG, Sheng-Yuan LIN, Hsin-Yu CHEN
  • Publication number: 20220367405
    Abstract: Methods and systems for improving fusion bonding are disclosed. Plasma treatment is performed on a substrate prior to the fusion bonding, which leaves residual charge on the substrate to be fusion bonded. The residual charge is usually dissipated through an electrically conductive silicone cushion on a loading pin. In the methods, the amount of residual voltage on a test silicon wafer is measured. If the residual voltage is too high, this indicates the usable lifetime of the silicone cushion has passed, and the electrically conductive silicone cushion is replaced. This ensures the continued dissipation of residual charge during use in production, improving the quality of fusion bonds between substrates.
    Type: Application
    Filed: February 8, 2022
    Publication date: November 17, 2022
    Inventors: Hong-Ta Kuo, Yen Hao Huang, I-Shi Wang, Ming-Yi Shen, Tzu-Ping Yang, Hsing-Yu Wang, Huang-Liang Lin, Yin-Tun Chou, Yuan-Hsin Chi, Sheng-Yuan Lin
  • Patent number: 11495709
    Abstract: A patterned epitaxial substrate includes a substrate and a plurality of patterns. The substrate has a first zone and a second zone surrounding the first zone. The first zone is disposed around a center of the substrate. The patterns and the substrate are integrally formed, and the patterns are disposed on the substrate. The patterns include a plurality of first patterns and a plurality of second patterns. The first patterns are disposed in the first zone. The second patterns are disposed in the second zone. Sizes of the first patterns are different from sizes of the second patterns.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 8, 2022
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Kuang-Yuan Hsu, Chien-Chih Yen, Yen-Lin Lai, Shen-Jie Wang, Sheng-Yuan Sun
  • Publication number: 20220347249
    Abstract: A composition for protecting liver, protecting intestines and enhancing immunity for freshwater fish is disclosed, including the following raw materials in parts by weight: 15˜27 parts of Andrographis herba, 18˜22 parts of Isatidis folium, 10˜15 parts of Polygonum hydropiper, 8˜12 parts of Rheum palmatum L., and 8˜12 parts of Galla chinensis. And the preparation and the application of the composition are disclosed. The composition of the disclosure has the effect of resisting bacteria, scavenge free radicals, clearing heat, detoxifying, preventing and treating enteritis and the like, which can effectively improve the immunity of the freshwater fish and ensure the health of the organism.
    Type: Application
    Filed: March 26, 2021
    Publication date: November 3, 2022
    Inventors: Jinjuan Wan, Hui Xue, Sheng Yuan, Aijun Xia, Yanhua Zhao, Meifang Shen
  • Publication number: 20220344358
    Abstract: A semiconductor device includes a substrate having an input/output (I/O) region, an one time programmable (OTP) capacitor region, and a core region, a first metal gate disposed on the I/O region, a second metal gate disposed on the core region, and a third metal gate disposed on the OTP capacitor region. Preferably, the first metal gate includes a first high-k dielectric layer, the second metal gate includes a second high-k dielectric layer, and the first high-k dielectric layer and the second high-k dielectric layer include an I-shape.
    Type: Application
    Filed: May 25, 2021
    Publication date: October 27, 2022
    Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Sheng-Yuan Hsueh
  • Publication number: 20220344854
    Abstract: A high-speed connector includes an insulating housing, and a first terminal assembly mounted in the insulating housing. The first terminal assembly includes a plurality of first terminals, a first base body and a first conductive film. The plurality of the first terminals include at least two first grounding terminals and at least two first signal terminals. At least one portion of a bottom of the first base body extends downward to form at least one first protruding portion. The at least two first signal terminals penetrate through the at least one first protruding portion. The first conductive film is covered to the at least one first protruding portion. The first conductive film has a first metal layer. The first metal layer is electrically connected with the at least two first grounding terminals to form a grounding structure.
    Type: Application
    Filed: January 3, 2022
    Publication date: October 27, 2022
    Inventors: SHENG-YUAN HUANG, CHUN-FU LIN, YUN-CHIEN LEE, PEI-YI LIN, YI-CHING HSU
  • Publication number: 20220344191
    Abstract: A wafer pod transfer assembly is provided. The wafer pod transfer assembly includes a wafer pod port to receive a wafer pod, a transfer axle coupled to the wafer pod port, a shaft receiver, a shaft coupled to the transfer axle and to the shaft receiver, a pin through the shaft receiver and through the shaft, wherein the pin comprises a first end and a second end, opposite the first end, and a pin buckle including a first loop and a second loop. The pin buckle is coupled to the pin, the first loop encircles the first end of the pin, and the second loop encircles the second end of the pin.
    Type: Application
    Filed: July 22, 2021
    Publication date: October 27, 2022
    Inventors: Chih-Wei CHOU, Sheng-Yuan Lin, Yuan-Hsin Chi, Yin-Tun Chou, Hung-Chih Wang, Yu-Chi Liu
  • Publication number: 20220344877
    Abstract: A high-speed connector includes an insulating housing, and a first terminal assembly mounted in the insulating housing. The first terminal assembly includes a plurality of first terminals including a plurality of first grounding terminals, a first base body, and a first shielding plate disposed under the first base body. The plurality of the first terminals are fastened to the first base body. The first shielding plate has a first base plate, a first metal layer and a plurality of first ribs. Several portions of a top surface of the first base plate extend upward to form the plurality of the first ribs. The first metal layer is a pattern with a plurality of pores. Several of the first grounding terminals contact with the first metal layer which is attached to top surfaces of the plurality of the first ribs to form a grounding structure.
    Type: Application
    Filed: September 13, 2021
    Publication date: October 27, 2022
    Inventors: PEI-YI LIN, YI-CHING HSU, SHENG-YUAN HUANG, CHUN-FU LIN
  • Publication number: 20220336732
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells by chemical reaction. The metal components are then removed by chemical reaction.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin YANG, Chung-Te LIN, Sheng-Yuan CHANG, Han-Ting LIN, Chien-Hua HUANG
  • Publication number: 20220337787
    Abstract: A wireless device having a multi-station mode provided by the present disclosure can act as a client/station. The wireless device has at least one wireless communication transceiver circuit. The wireless communication transceiver circuit makes the wireless device operate in the multi-station mode to link to multiple access point devices of hosts/APs simultaneously, and that is, the wireless device can be used as a work station of the access point devices of hosts/APs. The wireless device of the present disclosure can act as the work station of the access point devices at the same time or in the time-sharing manner, so it solves the technical problem that multiple transmitter devices of WLAN in the prior art cannot be used as the work station of the receiver device and the wireless network router (that is, the technical problem that each of multiple transmitter devices can only link to one access point).
    Type: Application
    Filed: April 16, 2021
    Publication date: October 20, 2022
    Inventors: Yi-Shing Chang, Luen-Sheng Yuan
  • Publication number: 20220336526
    Abstract: A micro light-emitting diode display panel including first and second substrates, micro light-emitting diodes, a wavelength conversion layer, a light-shielding pattern layer, a light filter layer, and an air gap is provided. The micro light-emitting diodes are disposed on the first substrate and respectively located in a plurality of sub-pixel areas. The micro light-emitting diodes are adapted to emit a light beam. The wavelength conversion layer is overlapped with at least a portion of the micro light-emitting diodes. The light beam is used to excite the wavelength conversion layer to emit a converted light beam. The light filter layer is disposed between the wavelength conversion layer and the second substrate and overlapped with the micro light-emitting diodes. The air gap is disposed between any two adjacent ones of any one of the micro light-emitting diodes, the second substrate, the wavelength conversion layer, and the light filter layer.
    Type: Application
    Filed: November 29, 2021
    Publication date: October 20, 2022
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Sheng-Yuan Sun, Po-Wei Chiu, Loganathan Murugan
  • Publication number: 20220336731
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin YANG, Chung-Te LIN, Sheng-Yuan CHANG, Han-Ting LIN, Chien-Hua HUANG
  • Publication number: 20220336479
    Abstract: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.
    Type: Application
    Filed: May 18, 2021
    Publication date: October 20, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Kuo-Hsing Lee, Chi-Horn Pai, Chang Chien Wong, Sheng-Yuan Hsueh, Ching Hsiang Tseng, Shih-Chieh Hsu
  • Publication number: 20220328504
    Abstract: A bit cell structure for one-time programming is provided in the present invention, including a substrate, a first doped region in the substrate and electrically connecting a source line, a second doped region in the substrate and having a source and a drain electrically connecting a bit line, a heavily-doped channel in the substrate and connecting the first doped region and the source of second doped region, and a word line crossing over the second dope region between the source and the drain.
    Type: Application
    Filed: May 14, 2021
    Publication date: October 13, 2022
    Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chi-Horn Pai, Chih-Kai Kang