Abstract: A semiconductor device of embodiments includes: a silicon carbide layer including a trench, a n-type first SiC region, a p-type second SiC region on the first SiC region, a n-type third SiC region on the second SiC region, a fourth SiC region of p-type between the first trench and the first SiC region, and a fifth SiC region electrically connecting the second SiC region and the fourth SiC region; and a gate electrode in the trench. The first trench has a first region extending in a first direction, a second region continuous with the first region, and a third region continuous with the second region and extending in the first direction. The second width of the second region in the second direction is larger than the first width of the first region in the second direction. The fifth SiC region is disposed in the second direction of the second region.

Abstract: In an entire intermediate region between an active region and an edge termination region, a p+-type region is provided between a p-type base region and a parallel pn layer. The p+-type region is formed concurrently with and in contact with p+-type regions for mitigating electric field near bottoms of gate trenches. The p+-type region has portions that face, respectively, n-type regions and p-type regions of a parallel pn layer in a depth direction Z and at the portions, has protrusions that protrude toward the parallel pn layer. N-type current spreading regions extend in the entire intermediate region from the active region and are between the p+-type region and the parallel pn layer, positioned between protrusions of the p+-type region. The impurity concentration of the n-type current spreading regions in the gate region is higher than that of those in other regions. Thus, avalanche capability may be enhanced.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region. The first electrode is in contact with each of the second impurity region and the third impurity region on the first main surface. The second electrode is in contact with the first impurity region on the second main surface. The second impurity region includes a first region and a second region disposed between the first region and the second main surface and in contact with the first region. An impurity concentration of the first region is more than or equal to 6×1016 cm?3.

Abstract: A method of manufacturing a superjunction silicon carbide semiconductor device is provided, enabling a reduction of the number of times a combination of epitaxial growth and ion implantation for forming a parallel pn structure is performed. In the method of manufacturing the superjunction silicon carbide semiconductor device, forming an epitaxial layer 2a, 2b of a second conductivity type on a front surface of a silicon carbide semiconductor substrate 1 of a first conductivity type and selectively forming semiconductor regions 4a, 4b of the first conductivity type by implanting nitrogen ions in the epitaxial layer are repeated multiple times, thereby forming the parallel pn structure.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extends in a direction opposite that of a depth of the trench and is connected to the p-type base layer.

Abstract: A semiconductor device of an embodiment includes a first trench extending in a first direction in a silicon carbide layer; a second trench and a third trench adjacent to each other in the first direction; a first silicon carbide region of n type; a second silicon carbide region of p type on the first silicon carbide region; a third silicon carbide region of n type on the second silicon carbide region; a fourth silicon carbide region of p type between the first silicon carbide region and the second trench; a fifth silicon carbide region of p type between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode, part of which is in the second trench, the first electrode contacting the first silicon carbide region between the fourth silicon carbide region and the fifth silicon carbide region; and a second electrode.

Abstract: A semiconductor device of an embodiment includes: a first trench located in a silicon carbide layer extending in a first direction; a second trench and a third trench adjacent to each other in the first direction; n type first silicon carbide region; p type second silicon carbide region on the first silicon carbide region; n type third silicon carbide region on the second silicon carbide region; p type fourth silicon carbide region between the first silicon carbide region and the second trench; p type fifth silicon carbide region between the first silicon carbide region and the third trench; p type sixth silicon carbide region shallower than the second trench between the second trench and the third trench and having a p type impurity concentration higher than that of the second silicon carbide region; a gate electrode in the first trench; a first electrode, and a second electrode.

Abstract: One object is to provide a semiconductor device capable of reducing loss during turn-on and degradation of forward voltage. A vertical MOSFET includes a semiconductor substrate 2 of a first conductivity type, a first semiconductor layer 1 of the first conductivity type, a second semiconductor layer 16 of a second conductivity type, first semiconductor regions 17 of the first conductivity type, first trenches 31 and a second trench 32, gate electrodes 20 provided in the first trenches 31 via a gate insulating film 19, and a Schottky electrode 29 provided in the second trench 32. The first trenches 31 are provided in a striped pattern, in a plan view and the second trench 32 surrounds the first trenches 31.

Abstract: One object is to provide a semiconductor device capable of suppressing forward voltage degradation and loss during turn-on. A vertical MOSFET includes a semiconductor substrate 2 of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer 16 of a second conductivity type, first semiconductor regions 17 of the first conductivity type, second semiconductor regions 3 of the second conductivity type, third semiconductor regions 4 of the second conductivity type, first trenches 31 and second trenches 32, gate electrodes 20 provided in the first trenches 31 via a gate insulating film 19, and Schottky metal 26 provided in the second trenches 32.

Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane parallel to a first direction and a second direction orthogonal to the first direction, and a second plane facing the first plane, the silicon carbide layer including a first trench and a second trench extending in the first direction; a gate electrode in the first trench and the second trench; a gate insulating layer; a gate wiring extending in the second direction, intersecting with the first trench and the second trench, connected to the gate electrode; a first electrode; a second electrode; and an interlayer insulating layer provided between the gate electrode and the first electrode. Neither the gate electrode nor the gate wiring is present between an end of the first trench in the first direction and the interlayer insulating layer.

Abstract: A control device causes an air conditioning apparatus to execute a temperature adjustment operation of causing a first temperature to approach a first target temperature at a target time point and causing a second temperature to approach a second target temperature at the target time point. The first temperature is a surface temperature of a partition portion including at least one of a floor, a wall, and a ceiling facing a target space. The second temperature is an indoor temperature of the target space.

Abstract: A semiconductor device of an embodiment includes: a first trench located in a silicon carbide layer extending in a first direction; a second trench and a third trench adjacent to each other in the first direction; n type first silicon carbide region; p type second silicon carbide region on the first silicon carbide region; n type third silicon carbide region on the second silicon carbide region; p type fourth silicon carbide region between the first silicon carbide region and the second trench; p type fifth silicon carbide region between the first silicon carbide region and the third trench; p type sixth silicon carbide region shallower than the second trench between the second trench and the third trench and having a p type impurity concentration higher than that of the second silicon carbide region; a gate electrode in the first trench; a first electrode, and a second electrode.

Abstract: A semiconductor device of an embodiment includes a first trench extending in a first direction in a silicon carbide layer; a second trench and a third trench adjacent to each other in the first direction; a first silicon carbide region of n type; a second silicon carbide region of p type on the first silicon carbide region; a third silicon carbide region of n type on the second silicon carbide region; a fourth silicon carbide region of p type between the first silicon carbide region and the second trench; a fifth silicon carbide region of p type between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode, part of which is in the second trench, the first electrode contacting the first silicon carbide region between the fourth silicon carbide region and the fifth silicon carbide region; and a second electrode.

Abstract: A superjunction silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a parallel pn structure in which epitaxially grown first column regions of the first conductivity type and ion-implanted second column regions of a second conductivity type are disposed to repeatedly alternate with one another, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, trenches, gate electrodes provided in the trenches via gate insulating films, another electrode, and a third semiconductor layer of the first conductivity type. The first column regions have an impurity concentration in a range from 1.1×1016/cm3 to 5.0×1016/cm3.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extends in a direction opposite that of a depth of the trench and is connected to the p-type base layer.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extending in a direction opposite that of a depth of the trench and connected to the p-type base layer.

Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.

Abstract: A silicon carbide semiconductor element includes n-type silicon carbide epitaxial layers formed on an n+-type silicon carbide semiconductor substrate, plural p base layers selectively formed in surfaces of the silicon carbide epitaxial layers, a p-type silicon carbide epitaxial layer formed in the silicon carbide epitaxial layer, and a trench penetrating at least the silicon carbide epitaxial layer. The silicon carbide semiconductor element also includes, in a portion of the silicon carbide epitaxial layer, a mesa portion exposing the p base layer. The silicon carbide semiconductor element further includes, between consecutive mesa side faces of the mesa portion, a flat portion substantially parallel to the silicon carbide substrate. The remaining thickness of the exposed p base layer is larger than 0.5 ?m and smaller than 1.0 ?m.

Abstract: In an n-type current diffusion region, a first p+-type region underlying a bottom of a trench (gate trench) is provided. In the n-type current diffusion region, a second p+-type region is provided between adjacent trenches, separated from the first p+-type region and in contact with the p-type base region. In the p-type base region, near a side wall of the trench, a third p+-type region is provided a predetermined distance from the side wall of the trench and is separated from the first and the second p+-type regions. The third p+-type region extends in a depth direction, substantially parallel to the side wall of the trench. A drain-side end of the third p+-type region is in contact with the n-type current diffusion region or protrudes a predetermined depth from the interface of the p-type base region and the n-type current diffusion region toward the drain.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, an upper second p+-type region, a lower second p+-type region and a first p+-type region are provided. The lower second p+-type region is provided orthogonal to a trench, and a total mathematical area regions that are between the first p+-type region and the p-type base layer and that include the n-type region is at least two times a total mathematical area of regions that are between the first p+-type region and the p-type base layer and that include the upper second p+-type region.