Abstract: In a semiconductor device having a first p+-type base region, a second p+-type base region, a high-concentration n-type region selectively formed in an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate; a p-type base layer formed on the n-type silicon carbide epitaxial layer; an n+-type source region and a p++-type contact region selectively formed in a surface layer of the p-type base layer; and a trench formed penetrating the p-type base layer and shallower than the second p+-type base region, in at least a part of the first p+-type base region, a region is shallower than the second p+-type base region as viewed from an element front surface side.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, first p+-type regions, and a second p+-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p+-type regions are provided with intervals therebetween along a width direction of the trench gate.

Abstract: A semiconductor device includes in an active region in which current flows, an n+-type silicon carbide epitaxial layer of a low concentration and formed on an n+-type silicon carbide substrate; a p-type channel region constituting a channel region; a trench contacting the p-type channel region and having embedded therein an oxide film and a gate electrode; a p+-type base layer arranged beneath the trench; a third n-type CSL layer region contacting the p-type channel region; a second n-type CSL layer region having a maximum impurity concentration higher than that of the third n-type CSL layer region, the maximum impurity concentration being farther on a substrate front side than a top of the p+-type base layer arranged beneath the trench is; and a first n-type CSL layer region contacting the second n-type CSL layer region and having a maximum impurity concentration lower than that of the second n-type CSL layer region.

Abstract: In forming an ohmic electrode on a back surface of an n-type SiC substrate, an n+-type semiconductor region is formed in a surface layer of the back surface of an n-type epitaxial substrate by ion implantation. In this ion implantation, the impurity concentration of the n+-type semiconductor region is a predetermined range and preferably a predetermined value or less, and an n-type impurity is implanted by acceleration energy of a predetermined range such that the n+-type semiconductor region has a predetermined thickness or less. Thereafter, a nickel layer and a titanium layer are sequentially formed on the surface of the n+-type semiconductor region, the nickel layer is heat treated to form a silicide, and the ohmic electrode formed from nickel silicide is formed. In this manner, a back surface electrode that has favorable properties can be formed while peeling of the back surface electrode can be suppressed.

Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.

Abstract: At bottom of a gate trench, a conductive layer is provided. A Schottky junction is formed along a side wall of the gate trench by the conductive layer and the n-type current spreading region. The Schottky junction constitutes one unit cell of a trench-type SBD. In the gate trench, a gate electrode is provided on the conductive layer, via an insulating layer. The gate electrode constitutes one unit cell of a trench-gate-type vertical MOSFET. In other words, one unit cell of the trench gate MOSFET and one unit cell of the trench-type SBD are disposed built into a single gate trench and oppose each other in a depth direction.

Abstract: Plural trenches are provided in a semiconductor substrate. First p+-type regions underlie bottoms of the trenches. A MOS gate is embedded in first trenches of the trenches and one unit cell of a trench-gate-type MOSFET is configured. One unit cell of a trench-type SBD is constituted by a Schottky junction formed by an n-type current spreading region and a conductive layer embedded in a second trench of the trenches. Between second trenches in which the trench-type SBD is embedded, at least two of the first trenches in which a MOS gate is embedded are disposed. A sum of widths of all first p+-type regions disposed in a MOS cell region C? that is substantially half of a region between the adjacent second trenches is in a range of about 2 ?m to 8 ?m.

Abstract: An information processing system includes circuitry that receives position information of first stroke information and second stroke information drawn on a display at different timing, adds additional information indicating a relationship of the received first stroke information and the received second stroke information to the received first stroke information, and generates, based on the position information of the received first stroke information, the position information of the received second stroke information and the added additional information, consecutive data used for displaying (playing) information drawn on the display as the first stroke information and the second stroke information, and a memory that stores the generated consecutive data.

Abstract: A semiconductor device includes an n-type silicon carbide epitaxial layer on a front surface of an n+-type silicon carbide substrate. A first p+-type base region is provided in the n-type silicon carbide epitaxial layer and a breakdown voltage structure region is provided in an outer periphery of an active region through which a main current flows. A distance between the first p+-type base region and a front surface of the n+-type silicon carbide substrate is smaller than a distance between the breakdown voltage structure region and the front surface of the n+-type silicon carbide substrate.

Abstract: On a surface of an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate, first and second p+-type base regions are formed in the n-type silicon carbide epitaxial layer, an n-type region is formed in the n-type silicon carbide epitaxial layer, a p-type base layer is formed on the n-type region, an n+-type source region and a p++-type contact region are formed in the p-type base layer, and a trench is formed to a position shallower than the second p+-type base region and penetrates the p-type base layer. A first sidewall angle of the trench at a position of the p-type base layer is 80° to 90° with respect to a main surface. A difference of the first sidewall angle and a second sidewall angle of the trench at a position deeper than a boundary of the p-type base layer and the n-type region is 1° to 25°.

Abstract: A silicon carbide semiconductor device, including a silicon carbide substrate, a drift layer provided on a front surface of the silicon carbide substrate, an embedded layer selectively provided in a surface layer of the drift layer, an epitaxial layer provided on the drift layer, a channel layer provided on the epitaxial layer, a source region selectively provided in a surface layer of the channel layer, a trench penetrating the source region and the channel layer and reaching the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a source electrode in contact with the channel layer and the source region, and a drain electrode provided on a rear surface of the silicon carbide substrate. The embedded layer is arranged underneath the trench in a depth direction. A longitudinal direction of the trench, which is perpendicular to the depth direction, is parallel to the off-direction of the silicon carbide substrate.

Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.

Abstract: In a first main surface side of a silicon carbide semiconductor base, a trench is formed. A second base region of a second conductivity type is arranged at a position facing the trench in a depth direction. An end (toward a drain electrode) of the second base region of the second conductivity type, and an end (toward the drain electrode) of a first base region of the second conductivity type reach a position deeper than an end (toward the drain electrode) of a region of a first conductivity type. Thus, the electric field at a gate insulating film at the trench bottom is mitigated, suppressing the breakdown voltage of the active region and enabling breakdown voltage design of the edge termination region to be facilitated. Further, such a semiconductor device may be formed by an easy method of manufacturing.

Abstract: On a front surface of a semiconductor base, an n?-type drift layer, a p-type base layer, an n++-type source region, and a gate trench and a contact trench penetrating the n++-type source region and the p-type base layer and reaching the n?-type drift layer are provided. The contact trench is provided separated from the gate trench. A Schottky metal is embedded in the contact trench and forms a Schottky contact with the n?-type drift layer at a side wall of the contact trench. An ohmic metal is provided at a bottom of the contact trench and forms an ohmic contact with the n?-type drift layer.

Abstract: In an n-type current diffusion region, a first p+-type region is provided under a bottom of a trench (gate trench). Further, in the n-type current diffusion region, a second p+-type region is provided between adjacent trenches so as to be separated from the first p+-type region and in contact with a p-type base region. In the p-type base region, a third p+-type region is provided near a side wall of the trench so as to be separated from the trench and first and second p+-type regions. A depth of the third p+-type region from an interface of the p-type base region and an n+-type source region does not reach the n-type current diffusion region. A shortest distance from the third p+-type region to the second p+-type region is at most a distance between the first and second p+-type regions.

Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, first p+-type regions, and a second p+-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p+-type regions are provided with intervals therebetween along a width direction of the trench gate.

Abstract: In a first main surface side of a silicon carbide semiconductor base, a trench is formed. A second base region of a second conductivity type is arranged at a position facing the trench in a depth direction. An end (toward a drain electrode) of the second base region of the second conductivity type, and an end (toward the drain electrode) of a first base region of the second conductivity type reach a position deeper than an end (toward the drain electrode) of a region of a first conductivity type. Thus, the electric field at a gate insulating film at the trench bottom is mitigated, suppressing the breakdown voltage of the active region and enabling breakdown voltage design of the edge termination region to be facilitated. Further, such a semiconductor device may be formed by an easy method of manufacturing.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In n?-type drift layer, an n-type region, a lower second p+-type region and a first p+-type region are provided. A part of the lower second p+-type region extending in a direction opposite that of a depth of the trench and connected to the p-type base layer.

Abstract: A p-type base region is constituted by first to fifth p-type base regions. The first p-type base region is provided deeper than gate trenches. The second p+-type base region is provided along side walls of a contact trench. The fourth p+-type base region is provided along a bottom of the contact trench and is exposed at the bottom of the contact trench. The fifth p-type base region is in contact with the second and fourth p+-type base regions, which have an impurity concentration higher than that of the fifth p-type base region. The fifth p-type base region is provided along the bottom of the contact trench and deeper than the fourth p+-type base region. In the fifth p-type base region, the third p++-type base region, which has an impurity concentration higher than that of the fifth p-type base region, is arranged.