Abstract: Device structures and methods are provided for fabricating vertical field-effect transistor devices with non-uniform thickness bottom spacers to achieve increased device performance. For example, a semiconductor substrate surface is etched to form semiconductor fins having bottom portions with concave sidewall surfaces that undercut upper portions of the fins. A doped epitaxial source/drain layer is formed on the concave sidewall surfaces, wherein portions of the doped epitaxial source/drain layer disposed between the fins have a raised curved surface. A bottom spacer layer is formed on the doped epitaxial source/drain layer, wherein portions of the bottom spacer layer disposed between the fins have a curved-shaped profile with a non-uniform thickness.

Abstract: A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.

Abstract: Vertical field effect transistor (VFET) structures and methods of fabrication with improved junction sharpness and reduced parasitic capacitance between the top source or drain and the surrounding metal gate includes a non-uniform top spacer in the top source or drain formed by an oxidation process. The top spacer has a thickness that is thinner at an interface between the top source or drain region and the vertically oriented channel region of the fin structure relative to the thickness of the top spacer layer away from the interface.

Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.

Abstract: A nanosheet field effect transistor device includes a semiconductor substrate including a stack of semiconductor nanosheets and a gate structure. The gate structure has an electrically conductive gate contact on the nanosheets and defines a channel region interposed between opposing source or drain (S/D) regions. The nanosheet field effect transistor further includes an electrically conductive cladding layer that encapsulates an outer surface of the S/D regions, and inner spacers on the sidewalls of the gate structure. The inner spacers are interposed between the cladding layer and the gate contact.

Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

Abstract: A method of forming a semiconductor structure includes patterning a hard mask layer over a top surface of a substrate. The method also includes forming a first portion of one or more vertical fins below the patterned hard mask layer. The method further includes forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins. The method further includes forming a second portion of the one or more vertical fins in the substrate below the top spacer and trimming sidewalls of the second portion of the one or more vertical fins. The method further includes forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins. The one or more vertical fins provide one or more vertical transport channels for one or more vertical transport field-effect transistors.

Abstract: BJT devices with 3D wrap around emitter are provided. In one aspect, a method of forming a BJT device includes: forming a substrate including a first doped layer having a dopant concentration of from about 1×1020 at. % to about 5×1020 at. % and ranges therebetween, and a second doped layer having a dopant concentration of from about 1×1015 at. % to about 1×1018 at. % and ranges therebetween, wherein the first and second doped layers form a collector; patterning a fin(s) in the substrate; forming bottom spacers at a bottom of the fin(s); forming a base(s) that wraps around the fin(s); forming an emitter(s) that wraps around the base(s); and forming sidewall spacers alongside the emitter(s). A BJT device is also provided.

Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.

Abstract: A self-assembled heteroepitaxial oxide nanocomposite film including alternating layers of a first metal oxide having a first melting point and a second metal oxide having a second melting point that differs from the first melting point is formed in an opening formed in a semiconductor substrate. After forming a metal or metal alloy via structure in the semiconductor substrate, first and second thermal treatments are performed to remove each layer of first or second metal oxide providing a nanoporous membrane.

Abstract: A method of forming a semiconductor device that includes forming at least two semiconductor fin structures having sidewalls with {100} crystalline planes that is present atop a supporting substrate; and epitaxially growing a source/drain region in a lateral direction from the sidewalls of each fin structure. The second source/drain regions have substantially planar sidewalls. A metal wrap around electrode is formed on an upper surface and the substantially planar sidewalls of the source/drain regions. Air gaps are formed between the source/drain regions of the at least two semiconductor fin structures.

Abstract: A method for fabricating a vertical transistor device includes forming a first plurality of fins in a first device region and a second plurality of fins in a second device region on a substrate. The first plurality of fins have a SiGe portion exposed above a top surface of the first region and a portion of the second plurality of fins are exposed above a top surface of the second region. The method further includes depositing a first GeO2 layer on the top surface of the device and over the exposed SiGe portion of the first plurality of fins and the exposed portion of the second plurality of fins.

Abstract: Semiconductor devices include a substrate layer and a semiconductor layer formed over the substrate layer. A dielectric layer fills a gap between the semiconductor layer and the substrate layer, on end faces of the semiconductor layer, and on a top surface of the semiconductor layer.

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a substrate, and forming one or more vertical transport field-effect transistors from the plurality of fins, the plurality of fins providing channels for the one or more vertical transport field-effect transistors. The method also includes forming a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack including a gate dielectric formed over the plurality of fins, a work function metal layer formed over the gate dielectric, and a gate conductor formed over the work function metal layer. The gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins.

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a substrate, and forming one or more vertical transport field-effect transistors from the plurality of fins, the plurality of fins providing channels for the one or more vertical transport field-effect transistors. The method also includes forming a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack including a gate dielectric formed over the plurality of fins, a work function metal layer formed over the gate dielectric, and a gate conductor formed over the work function metal layer. The gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins.

Abstract: A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions.

Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin on a substrate, and depositing a sidewall liner on exposed surfaces of the vertical fin. The method further includes removing a portion of the substrate below the sidewall liner to form a support pillar below the vertical fin. The method further includes laterally etching the support pillar to form a thinned support pillar, and forming a bottom source/drain layer on the substrate and the thinned support pillar, wherein the bottom source/drain layer has a non-uniform thickness.

Abstract: A semiconductor structure includes a substrate, a plurality of fins disposed over a top surface of the substrate, and a gate stack surrounding a portion of sidewalls of the plurality of fins. The plurality of fins include two or more active device fins comprising a semiconducting material providing vertical transport channels for respective vertical transport field-effect transistors, and two or more edge fins surrounding the two or more active device fins, the two or more edge fins comprising a dielectric material. Thicknesses of one or more layers of the gate stack surrounding the portion of the sidewalls of the two or more edge fins are different than thicknesses of the one or more layers of the gate stack surrounding the portion of the sidewalls of the active device fins. The vertical transport field-effect transistors provided by the active device fins have uniform threshold voltage.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.

Abstract: A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.