Patents by Inventor Shuichi Tanaka

Shuichi Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7830007
    Abstract: A semiconductor device includes n1 first interconnects (n is an integer larger than one) respectively formed on first electrodes and extending over a first resin protrusion, and n2 second interconnects (n2<n1) respectively formed on second electrodes and extending over a second resin protrusion. The first and second resin protrusions are formed of an identical material, have an identical width, and extend longitudinally. The first interconnects extends to intersect a longitudinal axis of the first resin protrusion, and each of the first interconnects has a first width W1 on the first resin protrusion. The second interconnects extends to intersect a longitudinal axis of the second resin protrusion, and each of the second interconnects has a second width W2 (W1<W2) on the second resin protrusion. The relationship W1×n1=W2×n2 is satisfied.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: November 9, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Shuichi Tanaka, Haruki Ito
  • Patent number: 7825518
    Abstract: A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate; and an interconnect electrically connected to the electrode and formed to extend over the resin protrusion. The interconnect includes a first portion formed on a top surface of the resin protrusion and a second portion formed on a side of a lower portion of the resin protrusion. The second portion has a width smaller than a width of the first portion.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: November 2, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Hideo Imai, Shuichi Tanaka
  • Publication number: 20100252829
    Abstract: A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
    Type: Application
    Filed: May 10, 2010
    Publication date: October 7, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shuichi TANAKA, Haruki ITO, Yasuhito ARUGA, Ryohei TAMURA, Michiyoshi TAKANO
  • Patent number: 7790595
    Abstract: A method for manufacturing a semiconductor device comprises (a) forming a resin layer that includes at least a plurality of a first and a second resin parts, being separated from each other, over a semiconductor substrate having an electrode pad and a passivation film; (b) forming a resin projection in which the first and the second resin parts are integrated by curing the resin layer; and (c) forming a conductive layer that is being connected electrically to the electrode pad and extending over the resin projection, wherein in process (a), the second resin part is formed at least between the electrode pad and the first resin part at a width less than the first resin part.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: September 7, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Tatsuhiko Asakawa, Shuichi Tanaka, Hideo Imai
  • Publication number: 20100171216
    Abstract: An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion.
    Type: Application
    Filed: March 22, 2010
    Publication date: July 8, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shuichi Tanaka
  • Patent number: 7741712
    Abstract: A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: June 22, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Shuichi Tanaka, Haruki Ito, Yasuhito Aruga, Ryohei Tamura, Michiyoshi Takano
  • Patent number: 7714436
    Abstract: An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: May 11, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Tanaka
  • Publication number: 20100109144
    Abstract: A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate; and an interconnect electrically connected to the electrode and formed to extend over the resin protrusion. The interconnect includes a first portion formed on a top surface of the resin protrusion and a second portion formed on a side of a lower portion of the resin protrusion. The second portion has a width smaller than a width of the first portion.
    Type: Application
    Filed: January 11, 2010
    Publication date: May 6, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hideo IMAI, Shuichi TANAKA
  • Patent number: 7671476
    Abstract: A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate; and an interconnect electrically connected to the electrode and formed to extend over the resin protrusion. The interconnect includes a first portion formed on a top surface of the resin protrusion and a second portion formed on a side of a lower portion of the resin protrusion. The second portion has a width smaller than a width of the first portion.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: March 2, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Hideo Imai, Shuichi Tanaka
  • Publication number: 20090317969
    Abstract: A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the semiconductor is improved.
    Type: Application
    Filed: September 2, 2009
    Publication date: December 24, 2009
    Applicant: Seiko Epson Corporation
    Inventor: Shuichi TANAKA
  • Patent number: 7629671
    Abstract: A semiconductor device including a semiconductor substrate having a plurality of electrodes, a resin protrusion formed on the semiconductor substrate, and an interconnect electrically connected to the electrodes and formed to extend over the resin protrusion. A depression is formed in a top surface of the resin protrusion. The interconnect has a cut portion disposed over at least part of the depression.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: December 8, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Tanaka
  • Patent number: 7601626
    Abstract: A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the semiconductor is improved.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: October 13, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Tanaka
  • Publication number: 20090242122
    Abstract: A method of forming a bonded structure comprises the steps of: mounting a semiconductor device having an electrode; a convexity protruding higher than the electrode and formed of a resin; and a conductive unit electrically coupled to the electrode and extending over the surface of the convexity, onto a specific substrate with an intermediary of a bonding material; and mounting the semiconductor device by hot pressing within a temperature range including the glass transition temperature of the resin.
    Type: Application
    Filed: May 29, 2009
    Publication date: October 1, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shuichi TANAKA
  • Patent number: 7576424
    Abstract: A semiconductor device including: a semiconductor substrate on which a plurality of electrodes are formed; a plurality of resin protrusions formed on the semiconductor substrate, arranged along a straight line, and extending in a direction which intersects the straight line; and a plurality of electrical connection sections formed on the resin protrusions and electrically connected to the electrodes.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: August 18, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Tanaka
  • Patent number: 7550437
    Abstract: The present invention provides a composition for safely and effectively preventing and treating digestive organs diseases, particularly, gastric ulcer, duodenal ulcer, gastritis, diarrhea, enteritis and the like. There is also provided a composition having a novel mechanism of action in order to solve the problems which was difficult to be solved by the side effect previously known mechanisms of action. More particularly, there is provided a pharmaceutical composition containing an ingredient which activates PAR-2 as an essential ingredient, which is useful for inhibiting gastric acid secretion, promoting digestive tract mucus secretion, protecting digestive tract mucosa, repairing tissue of digestive organs, and preventing and treating digestive organs diseases.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: June 23, 2009
    Assignee: Fuso Pharmaceutical Industries, Ltd.
    Inventors: Hiromasa Araki, Atsufumi Kawabata, Ryotaro Kuroda, Kazuaki Kakehi, Shuichi Tanaka, Kenzo Kawai, Sachiyo Nishimura, Hiroyuki Nishikawa
  • Patent number: 7524700
    Abstract: A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the semiconductor is improved.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: April 28, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Tanaka
  • Publication number: 20090051028
    Abstract: An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion.
    Type: Application
    Filed: August 6, 2008
    Publication date: February 26, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shuichi TANAKA
  • Publication number: 20090045509
    Abstract: An electronic device including: a semiconductor chip on which an integrated circuit is formed; an electrode formed on the semiconductor chip and electrically connected to the integrated circuit; a resin protrusion disposed on the semiconductor chip; an interconnect formed on the electrode and extending over the resin protrusion; a wiring board on which a wiring pattern is formed, the semiconductor chip being mounted on the wiring board so that part of the interconnect positioned over the resin protrusion faces and is electrically connected to the wiring pattern; and an adhesive that bonds the semiconductor chip and the wiring board. The resin protrusion is compressed in a direction in which the distance between the semiconductor chip and the wiring board decreases and is formed of a material having a negative coefficient of thermal expansion.
    Type: Application
    Filed: August 7, 2008
    Publication date: February 19, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shuichi TANAKA
  • Publication number: 20090032944
    Abstract: A semiconductor device includes n1 first interconnects (n is an integer larger than one) respectively formed on first electrodes and extending over a first resin protrusion, and n2 second interconnects (n2<n1) respectively formed on second electrodes and extending over a second resin protrusion. The first and second resin protrusions are formed of an identical material, have an identical width, and extend longitudinally. The first interconnects extends to intersect a longitudinal axis of the first resin protrusion, and each of the first interconnects has a first width W1 on the first resin protrusion. The second interconnects extends to intersect a longitudinal axis of the second resin protrusion, and each of the second interconnects has a second width W2 (W1<W2) on the second resin protrusion. The relationship W1×n1=W2×n2 is satisfied.
    Type: Application
    Filed: July 29, 2008
    Publication date: February 5, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shuichi TANAKA, Haruki ITO
  • Patent number: 7429704
    Abstract: Provided is an electronic component including a pad provided on an active surface of a rectangular chip substrate, a resin protrusion provided along sides of the chip substrate, and a conductive portion which is electrically connected to the pad and which is formed out of a conductive film covering the surface of the resin protrusion. The resin protrusion includes a protruded body extending linearly and a plurality of the resin protrusions are provided on at least one side of the chip substrate to form a clearance in an intermediate portion of the side.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: September 30, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Hiroki Kato, Shuichi Tanaka