Patents by Inventor Siddharth

Siddharth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Artificial intellegence prediction algorithm for generating an itemized statement of work and quote for home services based on two dimensional images, text, and audio
    Patent number: 10528962
    Abstract: Systems and methods for providing AI-based cost estimates for services are disclosed. The method may comprise receiving, at one or more processors, data from a scanning of a location, the scanning performed by one or more of a camera, a computer vision device, an inertial measurement unit, or a depth sensor. Data may be received, at one or more processors, related to the identification of one or more key elements at the location. An itemized statement and quote of work to be performed may be generated at one or more processors.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 7, 2020
    Assignee: YEMBO, INC.
    Inventors: Zachary Rattner, Siddharth Mohan
  • Method to position spindle precisely in turret type automatic winder
    Patent number: 10526163
    Abstract: The invention relates to an automatic turret type yarn winding device. The automatic bobbin changeover process involves winding of yarn on a bobbin, followed by rotation of the turret to bring an empty bobbin into the winding position. Pressure rollers are provided to ensure consistent and accurate winding. The accurate relative positioning of the bobbins and pressure rollers is important. Wear and tear and particulate dust may cause malfunctioning of winder systems which may affect accuracy of turret rotations and relative positioning of the bobbins and pressure rollers, especially when the turret rotation during bobbin changeover stage is done in a single rotation. The invention provides a device and a method to position spindle precisely in turret type automatic winder, especially to identify correct stationing position of turret spindle after reverse movement post doffing.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: January 7, 2020
    Inventor: Siddharth Lohia
  • Ergonomic IV systems and methods
    Patent number: 10525237
    Abstract: An IV catheter system may have a catheter component with a catheter hub, a cannula extending distally from the catheter hub, and a push feature adjacent to the catheter hub. The IV catheter system may also have a needle component with a needle hub, a needle extending distally from the needle hub along an axis, and a grip extending from the needle hub, generally parallel to the axis, with a pull feature. In the insertion configuration, the needle may be positioned within the cannula and the distal end of the needle hub may be seated in a needle port of the catheter hub. In the fluid delivery configuration, the needle may be positioned outside the catheter hub. The push and pull features may be positioned to facilitate manipulation with a single hand to move the IV catheter system from an insertion configuration to a fluid delivery configuration.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: January 7, 2020
    Assignee: Becton, Dickinson and Company
    Inventors: Jonathan Karl Burkholz, Bart D. Peterson, Stephen T. Bornhoft, Neville Chia, Siddharth Singh, Ralph L. Sonderegger, Bin Wang
  • REMOTE SYSTEM FOR AN AUTONOMOUS VEHICLE
    Publication number: 20200004239
    Abstract: A remote system for an autonomous vehicle, includes a receiver, a controller, and a display device. The receiver is configured to receive road information. The controller is programmed to receive input related to the road information and create a supervision zone when the road information impacts road drivability. The display device is disposed at a control center area and configured to display a visual indication on a map of the supervision zone.
    Type: Application
    Filed: December 22, 2017
    Publication date: January 2, 2020
    Inventors: Liam PEDERSEN, Siddharth THAKUR, Armelle GUERIN, Ali MORTAZAVI, Atsuhide KOBASHI, Mauro DELLA PENNA, Richard ENLOW, Andrea ANGQUIST, Richard SALLOUM, Stephen WU, Ben CHRISTEL, Shane HOGAN, John DENISTON, Jen HAMON, Sannidhi JALUKAR, Maarten SIERHUIS, Eric SCHAFER, David LEES, Dawn WHEELER, Mark ALLAN
  • INTEGRATED MULT-DIE PARTITIONED VOLTAGE REGULATOR
    Publication number: 20200006292
    Abstract: A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Beomseok Choi, Siddharth Kulasekaran, Kaladhar Radhakrishnan
  • PACKAGE STRUCTURE HAVING SUBSTRATE THERMAL VENT STRUCTURES FOR INDUCTOR COOLING
    Publication number: 20200006287
    Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein the inductor is at least partially embedded within the substrate. One or more thermal vent structures extend through at least one of the substrate or a board attached to the substrate. The one or more thermal vent structures provide a thermal pathway for cooling for the inductor.
    Type: Application
    Filed: July 2, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Michael J. HILL, Leigh E. WOJEWODA, Mathew MANUSHAROW, Siddharth KULASEKARAN
  • INTEGRATED CROSS-DOMAIN POWER TRANSFER VOLTAGE REGULATORS
    Publication number: 20200004282
    Abstract: An apparatus is provided, where the apparatus includes a first domain including first one or more circuitries, and a second domain including second one or more circuitries. The apparatus may further include a first voltage regulator (VR) to supply power to the first domain from a power bus, a second VR to supply power to the second domain from the power bus, and a third VR coupled between the first and second domains. The third VR may at least one of: transmit power to at least one of the first or second domains, or receive power from at least one of the first or second domains.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: Beomseok Choi, Siddharth Kulasekaran, Krishna Bharath
  • MULTI-LAYER SOLUTION BASED DEPOSITION OF DIELECTRICS FOR ADVANCED SUBSTRATE ARCHITECTURES
    Publication number: 20200006180
    Abstract: Embodiments include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a substrate, and a plurality of conductive features formed over the substrate. In an embodiment, a bilayer build-up layer is formed over the plurality of conductive features. In an embodiment, the bilayer build-up layer comprises a first dielectric layer and a second dielectric layer. In an embodiment, a surface of the first dielectric layer comprises depressions. In an embodiment, the second dielectric layer is disposed in the depressions of the surface of the first dielectric layer.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Andrew BROWN, Ji Yong PARK, Siddharth ALUR, Cheng XU, Amruthavalli ALUR
  • Dielectric Passivation for Electronic Devices
    Publication number: 20200006500
    Abstract: Dielectric super-junction transistors use combinations high dielectric relative permittivity materials and high-mobility materials. An associated electronic device includes a junction portion of a barrier layer adjacent a gate contact and a drain contact. A layered semiconductor device is configured with a junction dielectric permittivity that is greater than a channel dielectric permittivity in the channel layer. The junction portion has a dielectric structure that polarizes carriers within the junction portion such that excess charge on the gate is compensated by an opposite charge in the junction portion of the barrier layer proximate the gate. A sheet charge in the barrier layer is increased to form a depletion region with the channel layer that avoids a conductive parallel channel in the barrier layer to the drain contact.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Inventors: Siddharth Rajan, Zhanbo Xia, Caiyu Wang
  • SYSTEM AND METHOD FOR USING AN UNOBSTRUSIVE AND DISCRETE EMBEDDED BARCODE FOR DEBUGGING
    Publication number: 20200004661
    Abstract: Aspects of the present disclosure involve systems, methods, devices, and the like for generating an unobtrusive and discrete barcode used for debugging. In one embodiment, a system is introduced that enables the tracking of application interactions on a user device. The tracking can include the generation of a debug id which can include a discrete string used to describe locations, preferences, and interactions with a user device application. The string may then be converted into a corresponding barcode which can be discretely displayed on the user interface of the application. In another embodiment, the barcode may be captured and/or retrieved for use in debugging the application, in an instance where an application malfunction is encountered.
    Type: Application
    Filed: July 2, 2018
    Publication date: January 2, 2020
    Inventors: Sherman CHEN, Derek ANDERSON, Siddharth Reddy MALKIREDDY
  • INTEGRATED CIRCUIT STRUCTURES HAVING GERMANIUM-BASED CHANNELS
    Publication number: 20200006492
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Siddharth CHOUKSEY, Glenn GLASS, Anand MURTHY, Harold KENNEL, Jack T. KAVALIEROS, Tahir GHANI, Ashish AGRAWAL, Seung Hoon SUNG
  • Dynamic paging concatenation methods and systems
    Patent number: 10524230
    Abstract: Methods and systems disclosed herein can help to dynamically adjust the degree of or enable/disable concatenation of page messages, depending upon whether a user equipment is operating as a single radio LTE (SRLTE) device. An exemplary method involves a radio access network: (i) determining that a UE is configured to use a single radio system for both (a) data communication under a first air interface protocol, and (b) voice calls under a second air interface protocol that is different from the first air interface protocol, (ii) based at least in part on the determination, selecting a page-concatenation level to be used to page the first UE, and (iii) transmitting at least on page message to the UE according to the selected page-concatenation level.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: December 31, 2019
    Assignee: Sprint Spectrum L.P.
    Inventors: Siddharth S. Oroskar, Jasinder P. Singh
  • Methods and apparatus for active transparency modulation
    Patent number: 10522106
    Abstract: A viewing system is provided including an active transparency modulation film in the form of addressable arrays of electrochromic pixel structures. The viewing system may be used in, for instance, a head-mounted display (HMD) or head-up display (HUD). The film is located on one side of a viewing lens of the system and is selectively variable from opaque to transparent at certain regions on the lens to provide an opaque silhouetted image upon which a virtual image is projected. The viewing system including the film and pixel structure therefore provide improved viewing by minimizing the undesirable effects of image ghosting in a viewed scene.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: December 31, 2019
    Assignee: Ostendo Technologies, Inc.
    Inventors: Siddharth S. Hazra, Hussein S. El-Ghoroury
  • MUTATION PROFILE AND RELATED LABELED GENOMIC COMPONENTS, METHODS AND SYSTEMS
    Publication number: 20190392951
    Abstract: A mutation profile can be determined for an individual's DNA sequence or sequence segment that provides information about the evolutionary history of the DNA. This mutation profile can then be used with a machine learning classifier trained on other people's mutation profiles to determine probabilities that the individual has certain phenotypes. An example is cancer, where the probabilities of different types of cancer can be provided in a disease risk propensity.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 26, 2019
    Inventors: Siddharth JAIN, Bijan H.S. MAZAHERI, Netanel RAVIV, Jehoshua BRUCK
  • PACKAGE SUBSTRATE HAVING POLYMER-DERIVED CERAMIC CORE
    Publication number: 20190393109
    Abstract: Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.
    Type: Application
    Filed: March 30, 2017
    Publication date: December 26, 2019
    Inventors: Lisa Ying Ying CHEN, Lauren Ashley LINK, Robert Alan MAY, Amruthavalli Pallavi ALUR, Kristof Kuwawi DARMAWIKARTA, Siddharth K. ALUR, Sri Ranga Sai BOYAPATI, Andrew James BROWN, Lilia MAY
  • ELECTRICAL INTERCONNECTIONS WITH IMPROVED COMPLIANCE DUE TO STRESS RELAXATION AND METHOD OF MAKING
    Publication number: 20190393129
    Abstract: According to various embodiments of the present disclosure, an electrically conductive pillar having a substrate is disclosed. The electrically conductive pillar can comprise a first portion, second portion and a third portion. The first portion and/or third portion can be formed of an electrically conductive material that can be the same or different. The second portion can be intermediate and abut both the first portion and the third portion. The second portion can comprise a solder element formed of a second electrically conductive material that differs from the electrically conductive material and has a second stiffness less than a stiffness of the electrically conductive material.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 26, 2019
    Inventors: Siddharth K. Alur, Sri Chaitra Jyotsna Chavali
  • LOW Z-HEIGHT, ULTRA-LOW DIELECTRIC CONSTANT AIR CAVITY BASED AND MULTI-CORE/HIGHLY ASYMMETRIC ANTENNA SUBSTRATE ARCHITECTURES FOR ELECTRICAL PERFORMANCE IMPROVEMENTS IN 5G MM-WAVE APPLICATIONS
    Publication number: 20190393606
    Abstract: Embodiments include antennas, methods of forming antennas, and a semiconductor package. An antenna includes a feed port disposed in a substrate, and the feed port having a first patch and a second patch. The first patch is disposed on a top surface of substrate, and the second patch is disposed on a bottom surface of substrate. The antenna includes a photoimageable dielectric (PID) disposed on the bottom surface of substrate, where PID surrounds the second patch. The antenna includes a third patch disposed on PID, where the third patch is below the second patch. The antenna includes a cavity disposed between the second and third patches, where the cavity is enclosed by PID and third patch. An additional antenna includes a patch disposed on a first substrate, and a feed port disposed in a second substrate. This antenna includes a composite layer disposed between the first and second substrates.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Sri Chaitra CHAVALI, Siddharth ALUR, Sheng LI
  • Detection of email-related vulnerabilities
    Patent number: 10516692
    Abstract: Examples relate to detection of email-related vulnerabilities. The examples disclosed herein enable monitoring, at a runtime, application programming interface (API) calls made by a server-based application for the API calls related to at least one of a plurality of email protocols. A request to obtain a first set of data indicating a result of a vulnerability attack may be received from a vulnerability scanner. The examples disclosed herein enable identifying, at the runtime, an API call that has been made based on the vulnerability attack in response to receiving the request. The first set of data may be obtained, at the runtime, based on the API call. The examples disclosed herein further enable providing the first set of data to the vulnerability scanner to detect a vulnerability in the first set of data.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: December 24, 2019
    Assignee: Micro Focus LLC
    Inventors: Sasi Siddharth Muthurajan, Ronald Joseph Sechman
  • VIRTUAL COMPUTING INSTANCE TRANSFER PATH SELECTION
    Publication number: 20190384625
    Abstract: The disclosure provides an approach for selecting a path to use in transferring a virtual computing instance such as a virtual machine (VM), across data centers. In one embodiment, throughput and throttling information are sampled (e.g., per second) when VMs are transferred from a source data center to a destination data center, and the sampled information is used to construct histograms that provide performance profiles of the VM transfers. Such histogram information across a number of VM transfers can then be mined to determine trends. In turn, trends determined from historical histogram information may be extrapolated into the future to predict performance of a subsequent VM transfer operation and to select a path and/or destination storage and host pair to use for the VM transfer operation.
    Type: Application
    Filed: August 29, 2019
    Publication date: December 19, 2019
    Inventors: Siddharth EKBOTE, Leon CUI
  • REMOVAL OF NEAR DC ERRORS IN A PEAK-CONTROLLED BOOST CONVERTER USING A LOW-BANDWIDTH SECONDARY CONTROL LOOP
    Publication number: 20190386561
    Abstract: A method may include controlling switching behavior of switches of a switch-mode power supply based on a desired physical quantity associated with the switch-mode power supply, wherein the desired physical quantity is based at least in part on a slope compensation signal, generating the slope compensation signal to have a compensation value of approximately zero as seen by a compensation control loop of the switch-mode power supply, and modifying the slope compensation signal on successive switching cycles of the switch-mode power supply to account for differences in an output of the compensation control loop and an average current of an inductor of the switch-mode power supply in at least one phase of a switching period of a switching cycle of the switch-mode power supply.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 19, 2019
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Eric J. KING, Siddharth MARU, Thomas HOFF, Graeme G. MACKAY