Abstract: Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Abstract: An improved method that incorporates a user interface for a defibrillator (100) capable of being used with paddle electrodes (180) and adhesive pad electrodes (190). A shock delivery button (110) located on the defibrillator control panel delivers a shock through the pad electrodes. A second shock delivery button (210), located on the paddle electrodes, delivers a shock through the paddle electrodes. Both shock delivery buttons are configured with the same shape, operation and illumination in order to reduce user confusion.

Abstract: Disclosed herein are magnetic materials comprising rare earth nitrides and, more particularly, magnetic materials comprising multilayer-structured materials comprising one relatively soft and one relatively hard magnetic layer. The magnetic materials comprise a first ferromagnetic layer, a second ferromagnetic layer, and a blocking layer between and in contact with each of the first 5 and second ferromagnetic layers. The first and second ferromagnetic layers have different coercive fields. The first ferromagnetic layer comprises a first rare earth nitride material and the second ferromagnetic layer comprises a second rare earth nitride material. Also disclosed are methods for preparing the materials. The materials are useful in the fabrication of devices, such as GMR magnetic field sensors, MRAM devices, TMR magnetic field sensors, and magnetic 10 tunnel junctions.

Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Abstract: An integrated circuit architecture that provides a path having relatively low thermal resistance between one or more electronic devices and one or more thermal structures formed on an insulator layer on a substrate. Independent parallel thermal conduction paths are provided through the insulator layer, such as a buried oxide (“BOX”) layer, to allow heat to flow from the substrate layer to a collector column having a portion in common with a thermal structure disposed upon the BOX layer. In some cases, the substrate is a silicon substrate layer supporting the thermal structure and the collector column and a heat source, such as an electronic device (e.g., power amplifier, transistor, diode, resistor, etc.).

Abstract: A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.

Abstract: A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

Abstract: A wagering game system and its operations are described herein. In some embodiments, the operations can include detecting that one or more wearable computers are within a proximity range to a wagering game machine. In some examples, the operations further include determining one or more characteristics associated with the one or more wearable computers in response to the detecting that the one or more wearable computers are within the proximity range to the wagering game machine. In some examples, the operations further include providing a feature associated with a wagering game based on the one or more characteristics of the one or more wearable computers.

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

Abstract: A rotary cleaning apparatus for underwater cleaning including a housing, a battery, a motor and a flexible hub system. The flexible hub system includes a toroidal brush system coupled to a circular centrifugal pump assembly. The flexible hub system includes a flexible hub allowing the flexible hub system to bend out of plane. When the flexible hub system is rotated underwater at a curved surface, the brush system cleans the surface while the suction of the centrifugal pump assembly flexes the flexible hub system to evenly contact the surface.

Abstract: A terminal supporting apparatus 10 supports at least one of two ends of a control cable having an inner cable and an outer cable. The terminal supporting apparatus 10 includes: a hub 12 attached to an end of the outer cable, and having a flange on an outer periphery thereof; a cushion member 14 disposed to surround the outer periphery of the hub, and being in contact with the flange at both a front surface and a rear surface of the flange; and a housing 17 having a housing part that houses the cushion member. When an angle formed between an axis of the housing part and an axis of the hub is varied in a range of 0.0° to 6.0°, a diagonal static spring constant of the cushion member in an axial direction thereof may be in a range of 350 to 600 N/mm.

Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Abstract: An apparatus for guiding an autonomous vehicle towards a docking station including an autonomous vehicle with a camera-based sensing system, a drive system for driving the autonomous vehicle, and a control system for controlling the drive system. The apparatus includes a docking station including a first fiducial marker and a second fiducial marker, wherein the second fiducial marker is positioned on the docking station to define a predetermined relative spacing with the first fiducial marker, wherein the control system is operable to receive an image provided by the camera-based sensing system, the image including a representation of the first and second fiducial markers, and to control the drive system so as to guide the autonomous vehicle towards the base station based on a difference between the representation of the first and second fiducial markers in the received image and the predetermined relative spacing between the first and second fiducial markers.